# Technical Sessions

 PRIME 2018 Technical Sessions SMACD 2018 Technical Sessions
 TUESDAY, July 3rd 10:20-12:00 Data Converters Room #103  Chair: Günhan Dündar, Bogazici University, Turkey 10:20 Generalized Referenceless Timing Mismatch Calibration for Time-Interleaved ADCs A. Uran, M. Kilic, Y. Leblebici EPFL, Switzerland Calibration of time-interleaved analog-to-digital converters is a problem whose necessity and complexity increase with the number of interleaved channels. In this study, we develop a generic representation of the referenceless timing mismatch calibration scheme for N-channel TI-ADCs. We compare cross-correlation and mean absolute difference based approaches, and investigate the effect of increasing number of channels on the performance. We use both mathematical analyses and simulations to reveal degradation mechanisms, and discuss the extent to which this scheme is applicable. 10:40 A 6.5-μW 70-dB 0.18-μm CMOS Potentiostatic Delta-Sigma for Electrochemical Sensors J. Aymerich, M. Dei, L. Terés, F. Serra-Graells IMB-CNM (CSIC), Spain This paper presents the design of a low-power potentiostatic second-order continuous-time (CT) delta-sigma modulator DSM for the amperometric read-out and A/D conversion of electrochemical sensors. The proposed architecture reuses the sensor itself as a leaky integrator stage for shaping the quantization noise, resulting in a very compact and energy efficient read-out front end. Low-power CMOS circuits are also presented for the remaining analog blocks of the DSM loop. A design example in 0.18-Œºm CMOS technology is provided with a total area of 0.063mm¬≤. Post-layout simulations show a dynamic range of 70dB with an overall power consumption of 6.5ŒºW at 1.8-V supply. 11:00 11.7b Time-To-Digital Converter with 0.82ps resolution in 130nm CMOS Technology R. Granja1 M. Santos1 J. Guilherme2, N. Horta3 1Instituto de Telecomunicações, Portugal; 2Instituto Politécnico de Tomar, Portugal; 3Instituto Superior Técnico Lisboa, Portugal This paper describes a high-resolution 11.7b Time-to-Digital Converter (TDC) designed in a pure digital CMOS 130nm technology. The target architecture comprises a looped delay-line based on an inverter-based pulse-shrinking technique. The proposed technique can achieve a 0.82ps resolution with a dynamic range of 2.918ns, an integral nonlinearity (INL) of -2.4 to 2.11 and a differential nonlinearity (DNL) of -0.91 to 0.87 LSB. In addition, it occupies a low area of 0.14768 mm2. 11:20 A High-resolution ∆-Modulator ADC with Oversampling and Noise-shaping for IoT A. Correia1, P. Barquinha1, J. Marques2, J. Goes1 1Universidade NOVA de Lisboa, Portugal; 2S3 Semiconductors, Portugal This paper proposes a novel high-resolution delta-modulator with oversampling and noise-shaping suitable for industrial IoT systems. ''Inspired by a SAR ADC, this architecture uses an integrator in the digital domain, instead of the usual SAR logic. Combining adaptive-step delta-modulation with the adopted low/medium-resolution DAC scheme, an energy efficient A/D converter architecture is proposed, presenting encouraging results in comparison with the reported SAR algorithms. Behavioral simulations demonstrate a dynamic performance of 88 dB of SNDR, corresponding to an ENOB of 14.3 bits, for a 1 MHz input signal bandwidth and using an oversampling-ratio of 64. 11:40 A 12.4fJ-FoM 4-Bit Flash ADC Based on the StrongARM Architecture A. Almansouri, A. Alturki, H. Fariborzi, K. Salama, T. Al-Attar King Abdullah University of Science and Technology, Saudi Arabia This work proposes an efficient 4-bit flash ADC based on the StrongARM comparator architecture. The proposed design eliminates the need for the resistive ladder by systematically modifying the sizing of the input differential pair of each comparator. As a consequence, the area and the power consumed within the ladder is eliminated. Furthermore, a Helpee StrongARM circuit is introduced which enables operation at an input voltage below the threshold voltage of the transistor. An enhanced 1-out-of-15 decoder converts the thermometer code from the StrongARM and the Helpee StrongARM comparators into a 1-out-of-n code. The proposed 4-bit flash ADC architecture, simulated in 90nm standard CMOS technology, consumes 292 ¬µW at 1.6 GHz sampling frequency, and has an ENOB of 3.88 and FoM of 12.4 fJ/conv.step. 10:20-12:00 Applications of modeling and design techniques Room #10  Chair: Nuno Horta, Instituto de Telecomunicações / Instituto Superior Técnico - Universidade de Lisboa, Portugal 10:20 Bringing Analog Design Tools to Security: Modeling and Optimization of a Low Area Probing Detector Andreas Herrmann, Michael Weiner, Michael Pehl and Helmut Graeb. Technical University of Munich In this paper a probing detector consisting of digital gates is optimized. Probing attempt detectors are a solution for on-chip protection against probing of interconnects. They measure a wire and raise an alarm if an additional capacitance is recognized. The required additional circuitry for such detectors introduce area overhead. It copes with the tradeoff between low area overhead, low number of false alarms, and detectability of probes with very small capacitances. A simulation-based optimization of a specific probing detector architecture results in an improvement in probing sensitivity from 40fF to 20fF at low area overhead and with a low probability of false alarms. 10:40 Reliability Based Hardware Trojan Design Using Physics-Based Electromigration Models Chase Cook, Sheriff Sadiqbatcha, Zeyu Sun and Sheldon Tan. University of California, Riverside In recent years the concern over Hardware Trojans has come to the forefront of hardware security research as these types of attacks pose a real and dangerous threat to both commercial and mission-critical systems. One interesting threat model utilizes semiconductor physics, specifically aging effects such as Electromigration (EM). However, existing methods for EM-based Trojans based on empirical Black’s models can easily lead to performance degradation and less accuracy in Trojan’s activation prediction. In this paper, we study the EM-based Trojan attacks based on recently developed physics-based EM models. We propose novel EM attack techniques in which the EM-induced hydrostatic stress increase in a wire is caused by wire structure or layer changes without changing the current density of the wires. The proposed techniques consist of sink/reservoir insertion or sizing and layer switching techniques based on the early and late failure modes of EM wear-out effects. As a result, the proposed techniques can have minimal impact on circuit performance, which is in contrast with existing current-density based EM attacks. The proposed techniques can serve as both a trigger or payload for the EM attack on power/ground networks and signal and clock networks. 11:00 Metamodel-Based Performance Evaluation for an Electromechanical Automotive System Christine Forster, Jérôme Kirscher, Linus Maurer, Georg Pelz Infineon Technology To investigate how microelectronic products and applications interact, we propose a metamodelling approach, on top of behavioural modelling. The approach combines device-level with system-level simulations, in order to close the gap between microelectronic product design and related applications design. The methodology allows to check whether a microelectronic product complies with its requirements and is acceptable for operational use in the final system. 11:20 Analysis and Modeling of a Novel SDR-based High-Precision Positioning System Claudio Talarico1, Giovanni Piccinni2, Gianfranco Avitabile2 and Giuseppe Coviello2. 1Gonzaga University, 2Politecnico di Bari This paper presents a novel Software Defined Radio (SDR) architecture for the design of a high-precision positioning system to be used in medical applications. The proposed architecture is composed of a single mobile transmitter and four fixed receivers using a non-coherent demodulation scheme. The transmitted signal consists of a 100 MHZ 64-length OFDM symbol representing the coefficients of a Frank-Zadoff-Chu (FCZ) sequence. The proposed design has been validated in presence of severe multipath interferences. The accuracy achieved in evaluating the position of the target is always above 1.2 cm with a mean error of 6 mm and a standard deviation of 2.2 mm. 11:40 Digital Architecture and ASIC Implementation of Wideband Delta DOR Spacecraft Onboard Tracker Gian Carlo Cardarilli1, Luca Di Nunzio1, Rocco Fazzolari1, Marco Matta, Marco Re, Alberto Nannarelli2, Dario Gelfusa3, Simone Lorenzo3 and Spanò Sergio1. 1University of Rome Tor Vergata, 2Danish Technical University Lyngby, Denmark, 3Thales Alenia Space Italy The tracking of signals coming from an interplanetary spacecraft is very challenging because the signals are often distorted by various noise sources. There are several methods used for spacecraft tracking, including the Delta Direct One-Way Ranging, or ΔDOR, technique. In the past the European Space Agency (ESA) supported missions where a Narrowband ΔDOR was used, but, in more recent years, an innovative Wideband approach was proposed. In this work, we propose an ASIC prototype implementation of this new tracking technique called Wideband ΔDOR for the ESA X/Ka Deep Space Transponder. 10:20-12:00 Variability and Test Room #115  Chair: Fabio M. De Passos, University of Seville, Spain 10:20 Accelerating Electromigration Wear-out Effects Based on Configurable Sink-Structured Wires Sheriff Sadiqbatcha, Chase Cook, Zeyu Sun and Sheldon X.-D. Tan. University of California, Riverside In this work, we propose a novel electromigration (EM) wear-out acceleration technique for fast EM reliability- testing and aging-analysis of practical VLSI chips. The new acceleration technique is based on the observation that sink structures have a significant impact on the lifetime of multi- segment interconnect wires. We develop a new configurable sink-structured interconnect wire in which the current in the sink segment can be activated/deactivated dynamically during operation. Using this method, we show how an interconnect structure, which is initially immortal to EM effects, can be induced to fail very quickly. Furthermore, we use a robust failure scheme which considers both early and late failures depending on the wire topology and current direction. The most significant contribution of the proposed work is that it enables EM accelerated testing at low temperature and voltage. This feature enables the testing of EM wear-out in isolation without invoking other reliability effects which are also accelerated by the traditional stressing conditions. Using the proposed method, we can achieve a lifetime reduction from 10+ years to a few days, or even hours, at relatively low temperatures, which is very desirable for practical EM testing of typical nanometer CMOS ICs. 10:40 Variability Analysis Tool for CMOS Analog/RF Circuits: VariAnT Engin Afacan, Yigit Ender Avci and Omer Osman Demirbas. Kocaeli University Commercial EDA tools offer process, voltage, and temperature (PVT) variation analyses in order to estimate the variation effects on the circuit performance. However, many of them use primitive MC (random sampling) during generation of the uncertain design space, which results in excessively longer simulation times (days, weeks, even months). Furthermore, users have limited access to modify some important properties (i.e. sampling method, variation type, etc.) in such tools. In this study, a comprehensive, flexible, and user-friendly SPICE based variability analysis tool (VariAnT) is presented, which exhibits four different variation analyses: Monte Carlo, Worst Case, Voltage-Temperature, and Sensitivity. The developed tool includes two enhanced sampling approaches during MC analysis: quasi-random sapmling and Latin Hypercube sampling, which improves the efficiency by reducing the number of samples required for an quite accurate yield estimation. Furthermore, sensitivity analysis helps users to determine the most critical device(s), which is a valuable design insight to reduce the number of re-design iterations. 11:00 Automated massive RTN characterization using a transistor array chip Pablo Saraza-Canflanca1, Javier Diaz-Fortuny2, Antonio Toro-Frias1, Rafael Castro-Lopez1, Elisenda Roca2, Javier Martin-Martinez2, Rosana Rodriguez2, Montserrat Nafria2 and Francisco Fernandez1 1IMSE-CNM, 2UAB. In this work, a CMOS transistor array for the massive measurement of random telegraph noise (RTN), together with a dedicated experimental setup, is presented. The array chip, called ENDURANCE, allows the massive characterization of the RTN parameters needed for a complete understanding of the phenomenon. Additionally, some experimental results are presented that demonstrate the convenience of the setup. 11:20 Testability Analysis Based on Complex-Field Fault Modeling Giuseppe Fontana, Francesco Grasso, Antonio Luchetta, Stefano Manetti, Maria Cristina Piccirilli and Alberto Reatti. Department of information engineering, University of Florence Testability analysis of linear time-invariant networks under the single-fault scenario is considered in this paper. To this end an interesting technique is proposed which does not require the analytic expression of the input-to-output network function. It is based on a fault model in the complex plane. The validity of the developed method is proved through applicative examples. A comparison with other similar techniques is also included. 11:40 The Reactance Transformation for near sidelobes reduction: a comparison of windowing techniques Pietro Burrascano1, Stefano Laureti1 and Marco Ricci2. 1Università di Perugia, 2Università della Calabria When estimating the impulse response of a system, pulse compression provides a valuable tool to overcome limitations due to noisy measurement environment conditions. These conditions occur in many contexts, among which the non-destructive testing is of particular interest in the industrial field. In this case, pulse compression is quite often implemented through frequency-modulated chirp signals applied to sensors of various types, including ultrasound, Eddy Current and thermographic sensors. The use of Pulse Compression technology provides a considerable advantage from the point of view of reducing the effects of measurement noise: however, its direct application implies the introduction of side-lobes that accompany the desired response. A reduction of these side-lobes can be obtained through appropriate windowing techniques: in this paper, a windowing technique based on the Reactance Transformation, recently proposed by the authors, is compared with the windowing techniques most frequently used in NDT. 10:20-12:00 Analog Circuits I Atrium  Chair: Gianluca Giustolisi, University of Catania, Italy 10:20 Improved class-AB output stage for Sub-1 V fully-differential operational amplifiers A. Ria, S. Del Cesta, A. Catania, M. Piotto, P. Bruschi University of Pisa, Italy An existent architecture for low voltage class-AB output stages is analyzed finding critical issues for which effective original solutions are proposed. The approach has been applied to the design of a compact class-AB fully-differential operational amplifier, capable of operating at a supply voltage of 0.8 V, providing a maximum output current of 7.5 mA with only 156 uA of quiescent supply current. The proposed amplifier constitutes a convenient building block for switched-capacitor circuits and low-voltage sensor interfaces. The performances of the amplifier are demonstrated by means of electrical simulations performed on a prototype designed with the UMC 0.18 um CMOS process. The total estimated area of the cell is 0.023 mm2 10:40 A fully differential, 200MHz, programmable gain, level-shifting, hybrid amplifier/power combiner/test buffer, using pre-distortion for enhanced linearity V. Kampus1, T. Rang1, D. Knaller2, C. Fleischhacker2, M. Korak2, J. Kiss2 1Tallinn University of Technology, Estonia; 2Intel, Austria With the continuous advancement of standards in high-end telecommunication systems, requirements for analog circuitry have become ever more demanding. The new standards not only want to support better modulation schemes, demanding less noise with higher linearity, but also require increased bandwidth from analog circuitry. This paper describes a fully differential, programmable gain, baseband power combiner with a bandwidth of 200MHz, using pre-distortion for extra linearity, that offers also level-shifting and test buffer functionalities. The pre-distortion allows the improvement of linearity in the amplifier‚Äôs AB stage, what otherwise would be a limiting factor in rail-to-rail swing operations and lowering the maximum throughput. 11:00 New Resistor Free Current Mode Wheatstone Bridge Topologies with Intrinsic Linearity L. Safari, G. Barile, V. Stornelli, G. Ferri, A. Leoni University of L'Aquila, Italy In this paper two new topologies for current-mode Wheatstone bridge (CMWB) are presented. The circuits are based on two second generation voltage conveyors (VCII) as basic building blocks and two nMOS transistors operating as variable resistor. The outputs of both circuits are intrinsically linear function of ŒîR. Compared to previously reported CMWB circuits, the proposed topologies offer several advantages. Firstly, they do not require any extra voltage buffer at output i.e. the produced output voltage can be directly used in practical applications. Secondly, they do not employ any passive resistor while there are multiple grounded and floating resistors in other CMWBs. Thirdly, they have the capability to electronically control the gain without a significant impact on consumed power. To confirm the proposed theory, PSpice simulation results using 0.35¬µm CMOS technology parameters are presented. 11:20 A Fully Differential Charge-Sensitive Amplifier for Dust-Particle Detectors S. Kelz, T. Veigel, M. Grözing, M. Berroth University of Stuttgart, Germany This paper presents the design and measurements of a fully differential charge sensitive amplifier operating in the frequency range from 7 Hz to 300 kHz. In comparison to the typically employed single input transistor topology, the shown differential approach greatly simplifies the suppression of common mode noise. The theory of the fully differential charge sensitive amplifier and analytical rules for the correct sizing of the feedback resistor and the input transistor are derived. Finally a double-cascode-amplifier is presented, achieving an equivalent noise charge of 114 elementary charges rms in the 7 Hz to 300 kHz frequency band at 5.4 pF differential detector capacitance. The amplifier is realized in a 0.35 ¬µm standard CMOS technology and consumes 26.4 mW at 3.3 V supply voltage. 11:40 A ZTC-based 0.5V CMOS Voltage Reference Y. Wenger, B. Meinerzhagen TU Braunschweig, Germany This paper presents a voltage reference circuit operational from a 0.5V supply which is based on the zero-temperature coefficient (ZTC) operating point of a MOS transistor. The ZTC condition is reviewed and it is found that a MOSFET biased below its ZTC point with a PTAT current sourcecan yield a temperature stable output at this low supply voltage. With this idea in mind, a circuit which does not rely on the availability of special devices like Shottky diodes is designed in 130nm CMOS. Simulations show that this circuit generates an average reference voltage of 318mV from a 0.5V supply. The temperature coefficient is 154ppm/K and the voltage reference has a power supply rejection ratio (PSRR) of 41dB at DC. 14:00-16:00 SMACD EDA Competition I Room #103  Chair: Ralf Sommer, IMMS GmbH, Germany & Engin Afacan, Kocaeli University, Turkey 14:00 CEDA Presentation Vasilis Pavlidis IEEE CEDA VP Publicity 14:30 An Analog/RF Circuit Synthesis and Design Assistant Tool for Analog IP: DATA-IP Ezgi Kaya1, Engin Afacan2 and Gunhan Dundar1. 1Bogazici University, 2Kocaeli University In this paper, an analog circuit synthesis and design assistant tool is proposed. The developed tool employs an SPEA2 algorithm as a multi-objective optimization engine to generate Pareto-optimal Fronts (PoF) for a given design problem. An analog library serving as analog IP, was also constructed, which includes pre-optimized PoFs and extracted PoF models for different loading and power limitation conditions. Thus, the user can either generate a new PoF for her/his problem or use the pre-existing PoFs as well as the extracted models without running any optimization step. The developed tool can also be utilized for feasibility checking of a circuit, performance prediction, and topology selection. The tool gives the opportunity of visualization of the design solutions, by allowing the user to verify the Pareto-optimal points in the test benches, to observe the design speciﬁcations of a speciﬁc design solution. A graphical user interface (GUI) is developed to combine all these utilities. To demonstrate the developed tool, two different OTA topologies were examined and all parts of the tool were discussed in detail. 15:00 Antenna Modeling Technique for Digital Communication Systems Mohammed Almoteriy, Mohamed Sobhy and John Batchelor. University of Kent This paper demonstrates the characterization and modeling of an antenna to predict its effect when used in a digital communication system. The technique was applied to a commercial dual-band antenna. An equivalent circuit model was derived to characterize the antenna behavior in the frequency domain. A time domain system model was also derived to enable the estimation of the antenna effects in a digital system. The results show that the antenna caused symbol scattering and contributed to the error vector magnitude. 15:30 SETA: A CAD tool for Single Event Transient Analysis and Mitigation on Flash-based FPGAs Sarah Azimi1, Boyang Du1, Luca Sterpone1, David Merodio Codinachs2 and Luca Cattaneo3. 1Politecnico di Torino, 2European Space Agency, 3Microsemi Flash-based Field Programmable Gate Array (FPGA) devices are nowadays golden cores of many applications especially in space and avionic fields where reliability is becoming an important concern. In particular, for Flash-based FPGAs when adopted in those applications, the main concern is radiation-induced voltage glitched know as Single Event Transient (SET) in the combinational logic. In this work, a new CAD tool has been developed in order to evaluate the sensitivity of the implemented circuit regarding SET and to mitigate their effects. The proposed tool has been applied to an industrial design adopted by the EUCLID space mission including more than ten different modules. The experimental results demonstrated the feasibility and efficiency of proposed tool. 14:00-16:00 Modeling, Optimization and Characterization Room #10  Chair: Jiri Jakovenko, Czech Technical University Prague, Czech Republic 14:00 A low power Voice Activity Detector for portable applications G. Meoni, L. Pilato, L. Fanucci University of Pisa, Italy Voice Activity Detectors (VADs) are used to enhance performances and to reduce the activation rate of speech recognition and key-word spotting applications. The last aspect is crucial for portable applications because it allows to save energy, increasing battery life. During last decades, VADs have been realized through hardware solutions to increase their speed in processing and to reduce their power consumption. However, the hardware implementation often represents a limit on the choice of the features to use, limiting the performances on recognition. This paper shows a low-power and low-area serial logistic regression classifier which uses the frame-energy, the maximum absolute signal finite difference and the maximum absolute squared signal finite difference over a frame as features. The system has been implemented on IGLOO nano Field Programmable Gate Array (FPGA), leading to power consumption of 0.559 mW and offering acceptable performances for its use as a preprocessor for speech recognition systems or a more sophisticated software VAD. 14:20 Fractional-order Hartley oscillator A. Agambayev1, A. Kartci2, A. Hassan1, N. Herencsar2, H. Bagci1, K. Salama1 1King Abdullah University of Science and Technology, Saudi Arabia; 2Brno University of Technology, Czech Republic A fractional-order capacitor (FOC) is developed using the Molybdenum disulfide mixed ferroelectric polymer composite. The fabricated FOC exhibits constant phase over 5 decades between 100 Hz-10 MHz, which is the reported broadest dynamic range so far. Furthermore, it is shown that oscillation frequency of the fractional-order Hartley oscillator built using the fabricated FOC is 10 times higher than the frequency of conventional Hartley oscillator counterpart. 14:40 System Level simulation framework for the ASICs development of a novel particle physics detector A. Caratelli1, S. Scarfì1, D. Ceresa2, K. Kloukinas2, Y. Leblebici1 1EPFL, Switzerland; 2CERN, Switzerland The simulation of the passage of particles through matter using Monte Carlo methods is broadly used in the development of particle detectors for high energy physics experiments. To develop the readout electronics for the Compact Muon Solenoid (CMS) experiment at CERN, and to assist the design of the on-detector ASICs, a simulation framework was build capable to link the physics Monte Carlo simulations platforms with an industry standard EDA simulation tools. This contribution focuses on the implementation of the simulation framework based on the System Verilog language and the Universal Verification Methodology (UVM). The simulation results that guided the development of the ASICs and the choice of the final architecture are presented. 15:00 A Bayesian indicator for Run-to-Run performance assessment in semiconductor manufacturing T. Korabi1,3, G. Graton2,3, E. El Adel3, M. Ouladsine3, J. Pinaton1 1STMicroelectronics, France; 2Ecole Centrale Marseille, France; 3University of Aix-Marseille, France In this paper, an indicator based on the Bayesian theory is proposed. This indicator is used for assessing the performances of Run-to-Run controllers. The indicator is calculated by analyzing four main points: the output/target error, the output dispersion, the out of tolerance (oot) rate and the industrial risk. The proposed Bayesian method has been tested on all the Run-to-Run loops of a real semiconductor manufacturing foundry. 15:20 UTBB FD-SOI Circuit Design using Multifinger Transistors: A Circuit-Device Interaction Perspective A. Sharma1, N. Alam2, A. Bulusu1 1Indian Institute of Technology Roorkee, India; 2Aligarh Muslim University, India This paper examines and models the performance of mlutifinger Ultra-Thin Box and Body Fully-Depleted (UTBB FD-SOI) MOSFETs in the presence of process induced mechanical stress. We model the channel stress and effective drive current (Ieff ) in a multifinger FDSOI MOSFET (Si channel NMOS and SiGe channel PMOS) as a function of the number of fingers (NFs). The proposed Ieff model predicts the performance (i.e. Ieff ) of Inverter/NAND-2/NAND-3 with a maximum error of 7% compared to Sentaurus TCAD simulations. We show that as the NFs in an NMOSFET increases from 1 to 12, Ieff per micrometer width increases by 36% and subsequently saturates. This is due to the increase in the channel stress with the NFs, which is similar to as observed in the bulk-CMOS technology. However, due to high biaxial stress, a PMOSFET‚Äôs (SiGe channel) performance changes only marginally with the NFs. This is because the improvement in hole mobility saturates at high biaxial stress values. We also show that the FO4 delay of an inverter reduces by 16.67% when twelve-finger devices are used to design the inverter rather than single finger devices. Finally, using our stress model and Ieff for an inverter/NAND/NOR cells, we propose a modified logical effort methodology (LEM)for combinational data-paths which incorporates multifinger effects in FDSOI MOSFETs. A 5-stage data-path designed using our LEM results in 14.3% improvement in total active area and 7% reduction in leakage power without a loss in speed compared to conventional technique. 15:40 Let's make it Noisy: A Simulation Methodology for adding Intrinsic Physical Noise to Cryptographic Designs K. Nawaz, L. Van Brandt, F. Standaert, D. Flandre UCLouvain, Belgium Noise in digital circuits for the sake of performance has always been minimized in typical designs. However, for cryptographic applications, increased noise could be beneficial. It can be used effectively to reduce the mathematical SNR (signal-to-noise ratio) further and make it more difficult for the adversary to gather useful information from the side channel leakage data. In this paper, we introduce a methodology to exploit the intrinsic physical noise (i.e. flicker and thermal noise) at the circuit level and use the obtained values in a relevant cryptographic context. Our simulations show that the calculated cryptographic noise values are in close agreement with the noise levels extracted from noisy distributions using transient noise analysis. Consequently, this noise is shown to increase with the number of transistors or the supply voltage. 14:00-16:00 Circuits for Memories and Security Room #115  Chair: Robert Kvacek, ASICentrum, Czech Republic 14:00 Analysis on Sensing Yield of Voltage Latched Sense Amplifier for Low Power DRAM S. Kim, B. Song, T. Oh, S. Jung Yonsei University, South Korea Various types of sense amplifiers are widely used in memory products. In this paper, we have studied on the optimization of a voltage latched sense amplifier (VLSA) with 65nm CMOS process for low-power DRAM. In particular, we have classified sensing failure into the offset failure and the latch-delay failure, and have found that the latch-delay failure becomes even worse at low supply voltages below 1.0V. We also found that conventional NMOS-driven sensing operation was no longer effective on VLSA for low supply voltage, and investigated various methods to decrease the latch-delay failure probability. 14:20 The key impact of incorporated Al2O3 barrier layer in W-based ReRAM switching performance E. Shahrabi1, C. Giovinazzo2, J. Sandrini1, Y. Leblebici1 1EPFL, Switzerland; 2Politecnico di Torino, Italy In this article, we inspected the bipolar resistive switching behavior of W-based ReRAMs, using HfO2 as switching layer. We have shown that the switching properties can be significantly enhanced by incorporating an Al2O3 layer as a barrier layer. It stabilizes the resistance states and lowers the operating current. Al2O3 acts as an oxygen scavenging blocking layer at W sides results in the filament path constriction at the Al2O3/HfO2 interface. This leads to the more controllable reset operation and consecutively the HRS properties improvement. This allows the W/Al2O3/HfO2/Pt to switch at 10 times lower operating current of 100 uA and 10 times higher memory window compared to the W/HfO2/Pt stacks. The LRS conduction of devices with the barrier layer is in perfect agreement with the F-N tunneling model. 14:40 A Variability-Aware Analysis and Design Guideline for Write and Read Operations in Crosspoint STT-MRAM Arrays Y. Belay, A. Cabrini, G. Torelli University of Pavia, Italy Benefiting from emerging resistance-switching memory technologies, crosspoint array has become an attractive array architecture to obtain high storage density. Among the emerging technologies, Spin-Transfer Torque Magnetic Memory(STT-MRAM) is a potential candidate as storage class memory (SCM) or static/dynamic RAM replacement due to its high write speed, scalability and other interesting characteristics. In this paper, we present a variation-aware comprehensive analysis of the boundary conditions for write and read requirements for the implementation of crosspoint STT-MRAM Arrays. The results of the analysis are very useful as a design guide and for choosing a suitable selector device for Crosspoint STT-MRAM arrays. 15:00 A Simulated Approach to Evaluate Side Channel Attack Countermeasures for the Advanced Encryption Standard L. Sarti, L. Baldanzi, L. Crocetti, B. Carnevale, L. Fanucci University of Pisa, Italy Modern networks have critical security needs and a suitable level of protection and performance is usually achieved with the use of dedicated hardware cryptographic cores. Although the Advanced Encryption Standard (AES) is considered the best approach when symmetric cryptography is required, one of its main weaknesses lies in its measurable power consumption. Side Channel Attacks (SCAs) use this emitted power to analyze and revert the mathematical steps and extract the encryption key. In this work we propose a simulated methodology based on Correlation and Differential Power Analysis. Our solution extracts the simulated power from a gate-level implementation of the AES core and elaborates it using mathematical-statistical procedures. An SCA countermeasure can then be evaluated without the need for any physical circuit. Each solution can be benchmarked during an early step of the design thereby shortening the evaluation phase and helping designers to find the best solution during a preliminary phase. The cost of our approach is lower compared to any kind of analysis that requires the silicon chip to evaluate SCA protection. 15:20 Enabling Secure Boot Functionality by using Physical Unclonable Functions K. Müller, R. Ulrich, A. Stanitzki, R. Kokozinski Fraunhofer IMS Duisburg, Germany A firmware encryption for embedded devices can prevent the firmware from being read out to clone the device to a counterfeited one or to steal the intellectual property of the software developer. Also the integrity is ensured to hinder an attacker from manipulating the firmware to a malicious one. In this work, a cryptographic concept to implement a Secure Boot functionality using the intrinsic properties of a specific hardware device is shown. After describing the Physical Unclonable Function and the cipher used for the implementation, the key generation algorithm is explained. Further, the function of the crypto-module inside the system architecture and the secure boot sequence are described. 15:40 Encryption of test data: which cipher is better? M. Da Silva, E. Valea, M. Flottes, S. Dupuis, G. Di Natale, B. Rouzeyre LIRMM, France Testing is a mandatory step in the Integrated Circuit (IC) production because it ensures the required quality of the devices. The most common solution for easing IC testing is the scan chain insertion. This way, a tester can control and observe the internal states of the circuit through dedicated pins. However, a malicious user can exploit this infrastructure in order to extract secret information stored inside the chip. This is the case for cryptographic circuits where partially encrypted results can be observed by shifting out the scan content and exploited to retrieve secret keys. Existing countermeasures consist in encrypting the scan content, ensuring the confidentiality of the exchanged messages between the circuit and the tester. The encryption techniques that have been proposed so far rely on the use of two different ciphers: stream ciphers and block ciphers. In this paper, we present pros and cons of both solutions in terms of security and performance. The purpose is to provide an overview of the state-of-the-art in test data encryption and to give elements of comparison between the two ciphers. 14:00-16:00 SS Latest advances in variability impact on devices and circuits functionality Atrium  Chair: Francisco V. Fernández, University of Seville, Spain 14:00 A Model Parameter Extraction Methodology Including Time-dependent Variability for Circuit Reliability Simulation Javier Diaz-Fortuny1, Pablo Saraza-Canflanca2, Antonio Toro-Frias2, Rafael Castro-Lopez2, Javier Martin-Martinez1, Elisenda Roca2, Rosana Rodriguez1, Francisco V. Fernández2 and Montserrat Nafria1. 1UAB, 2IMSE-CNM, In current CMOS advanced technology nodes, accurate extraction of transistor parameters affected by timedependent variability, like threshold voltage (Vth) and mobility (μ), has become a critical issue for both analog and digital circuit simulation. In this work, a precise VTH0 and U0 BSIM parameters extraction methodology is presented, together with a straightforward IDS to VTH0 shift conversion, to allow the complete study of aging device effects for reliability circuit 14:20 Voltage Adaptation under Temperature Variation Hussam Amrouch1, Behnam Khaleghi2 and Jörg Henkel1. 1Karlsruhe Institute of Technology, 2University of California San Diego The maximum delay of a processor is subject to both temperature (T) and voltage (V ) jointly. Therefore, there is the prospect of reducing V at runtime whenever T is below the worst-case temperature without violating the predetermined timing constraints, instead of employing throughout a conservative V that corresponds to Tworst. Hence, the efficiency can be maximized, while still accounting for temperature variation at runtime, without sacrificing reliability (i.e. no trade-offs). While there are few existing techniques that consider the correlation between T and V , our work is the first to address the key challenge of how the small, yet sufficient voltage can be accurately obtained in which timing constraints at runtime are assuredly fulfilled. To achieve that, we model the delay of processor under the joint effects of T and V through creating cell libraries that contain the detailed delay information of gates/cells at a wide variety of T and V cases. Our libraries are compatible with existing commercial EDA tools (e.g., Synopsys), which enables us to employ standard tool flows, even though they were not designed for that purpose, in order to seamlessly obtain the correlation between T and V in any circuit regardless its complexity (e.g., full processor). Based on our modeling of the correlation between T and V from the physical level to circuit level, we implement at the system level a temperature-guided voltage adaptation technique that tunes the voltage at runtime following temperature variations leading to a considerable reduction in power. 14:40 Lifetime Calculation Using a Stochastic Reliability Simulator for Analog ICs Antonio Toro-Frías1, Pablo Martín Lloret1, Javier Martin Martinez2, Rafael Castro Lopez1, Elisenda Roca1, Rosana Rodríguez2, Montserrat Nafria2 and Francisco V Fernández Fernández 1. 1IMSE-CNM, 2UAB With the downscale of integration well into the nanometer scale, designers have to take into account not only the performance of circuits due to time-zero variability but also the degradation due to time-dependent. To evaluate the impact of variability in the performance of the circuit, a critical metric is the time-dependent yield, the percentage of designs that operate correctly with respect to a set of performance constraints and that, in presence of time-dependent variability, varies over time. With this metric, the lifetime of the circuit, or the time the circuit is working within a pre-defined yield threshold, is another crucial metric, even fundamental in many applications that require a high degree in accuracy for its calculation. This work proposes a new efficient simulation methodology to estimate the lifetime using a stochastic reliability simulator that can provide accurate yield and lifetime metrics for analog circuits while keeping CPU times low. 15:00 Yield Approximation of Analog Integrated Circuits under Time-Dependent Variability Theodor Hillebrand, Maike Taddiken, Steffen Paul and Dagmar Peters-Drolshagen. University of Bremen In this paper an approximation technique for the time-depend yield of analog integrated circuit is presented. Due to the interaction of aging effects and process variations the yield approximation in early design stages can become very time consuming and hampers the quantity of explorative analysis. The here proposed method is based on the pre-computed analyses of basic analog blocks and uses the small signal behavior in order to approximate the yield. The method is evaluated at the example of a two-stage Miller-OTA 15:20 Optimizing Datapaths for Near Threshold Computing Mohammad Saber Golanbari and Mehdi B. Tahoori. Karlsruhe Institute of Technology Reducing the energy consumption of VLSI circuits is a crucial objective for many modern applications such as Internet of Things (IoT). The so called Near-Threshold Computing (NTC) offers about one order of magnitude improvement in the energy efficiency by lowering the supply voltage of a circuit down to the threshold voltage of transistors. As a result of this aggressive voltage scaling, the relative contributions of dynamic and leakage power consumptions to the overall power consumption of a circuit become comparable. However, the aggravated impact of variability sources (20x more) in such a low voltage range hinders the reliability of the NTC circuits, posing an important design challenge. As the assumptions for the power consumption profiles and variation impacts in the NTC are totally different from those of the nominal operating voltage, new optimization techniques are required for power/energy optimization and variability mitigation. In this paper, we discuss cross-layer design techniques for functional units suitable for mitigating variability in the near-threshold voltage regime. As a case study, we evaluate the effectiveness of the proposed techniques on a 64-bit Arithmetic Logic Unit (ALU) by considering circuit, micro-architecture, and architecture level design. 15:40 Design considerations of an SRAM array for the statistical validation of time-dependent variability models Pablo Saraza-Canflanca1, Daniel Malagon1, Fabio Passos1, Antonio Toro1, Juan Nuñez1, Javier Diaz-Fortuny2, Rafael Castro-Lopez1, Elisenda Roca1, Javier Martin-Martinez2, Rosana Rodriguez2, Montserrat Nafria2 and Francisco V. Fernandez1. 1IMSE-CNM, 2UAB Modeling and characterization of time-dependent variability phenomena as well as the simulation of their impact on circuit operation have attracted considerable efforts. This paper digs into the validation of compact models and simulation tools in the real operation of circuits. One of the most popular blocks, the 6T SRAM, is proposed for this purpose and a test chip containing an SRAM array is designed. The array allows individual access to each SRAM cell, the application of accelerated aging tests as well as the characterization of common performance metrics. 16:20-17:40 Power Circuits and Harvesting Room #103  Chair: Pavel Krejci, Allegro MicroSystems, Czech Republic 16:20 A CMOS gate driver with ultra-fast dV/dt embeedded control dedicated to optimum EMI and turn-on losses management for GaN power transistors P. Bau1,2, M. Cousineau1, B. Cougo2, F. Richardeau1, D. Colin3, N. Rouger1 1University of Toulouse, France; 2IRT Saint Exupéry, France; 3Association des industriels PRIMES, France In this paper, a CMOS gate driver in 180nm technology is presented. The gate driver implements an integrated and independent ultra-fast dV/dt control circuit dedicated to manage switch-on transients for GaN HEMT technology. To mitigate a detrimental effect in EMI spectrum for wide bandgap transistors, a novel method to reduce dV/dt without increasing so much switching losses is proposed. A comprehensive benchmark with the classical method is also presented, where the gate driver resistance is typically adjusted. Simulations are conducted to show the feasibility of the proposed method and the amount of switching energy that can be saved. Time response of a feedback loop lower than 200ps are expected. The preliminary characterization of the integrated CMOS circuit is shown. 16:40 Design of a SIBO DC-DC Converter for AMOLED Display Driving F. Boera, A. Salimath, E. Bonizzoni, F. Maloberti University of Pavia, Italy This paper describes a Single Inductor Bipolar Outputs (SIBO) DC-DC converter for Active Matrix Organic Light Emitting Diode (AMOLED) displays. The circuit is able to generate with a single inductor both the positive and the negative voltage necessary to turn on the AMOLED pixels and does not require the addition of post-regulation techniques. The circuit works with an input battery voltage ranging from 2.4 V to 4.9 V, compliant with Li-Ion batteries, and is able to generate +5 V and -6 V. The maximum output current delivered to the load is 0.6 A. The switching frequency is 2 MHz and the control loop has been implemented in Voltage Control Mode (VCM). The effectiveness of the single inductor based scheme has been verified at the behavioral level in Matlab-Simulink. 17:00 A human body powered sensory glove system based on multisource energy harvester A. Leoni1, V. Stornelli1, G. Ferri1, V. Errico2, M. Ricci2, A. Pallotti2, G. Saggio2 1University of L'Aquila, Italy; 2University of Roma Tor Vergata, Italy In this work we present and evaluate a multi-source power management system, based on human body energy harvesting, to extend the battery lasting of an electronic sensory glove, used to measure flexion/extension, abduction/adduction movements of fingers of the hand. The system exploits heat of the human forearm and pressure impressed by the foot heel during walking, so to gather additional energy. The aim is to allow hours of energy-autonomy for the user working with the sensory glove. Such a glove is equipped with a number of flex sensors which furnish data from finger movements, acquired and pre-processed by a microcontroller, and wireless sent to a Personal Computer for analysis, visualization and storage purposes. The multi-source harvester is based on vibrational and thermic sources. Prototype discrete element boards were designed and tested for the microelectronics integration. Measurement results demonstrate how the overall system extends the battery lasting time up to 20%. 17:20 HW platform for BMS algorithm validation L. Buccolini, F. Garbuglia, M. Unterhorst, M. Conti Universitá Politecnica delle Marche, Italy Lithium batteries are more and more used for energy storage. They need to be controlled by some battery management system (BMS) to maintain the batteries working in a safety range, estimate the state of charge, the state of health and to maximize the energy stored. Software simulation allows to improve the BMS algorithms but they need to be validated on real BMS and cells. This paper presents an HW platform composed by a custom, open-source BMS with a standard Arduino Uno compatible pinout, a battery charger, six lithium cells, and the software that handle the test. The platform is validated by using a passive cells balancing algorithm and a charging algorithm that interacts between them. 16:20-17:20 Design with Non-Conventional and Emerging Devices Room #10  Chair: Mark Po-Hung Lin, National Chung Cheng University, Taiwan 16:20 Design of Logic Gates by Using a Four-Gate Thin Film Transistor (FG TFT) Sadık İlik, Fikret Başar Gencer and Mustafa Berke Yelten. Istanbul Technical University Electronics and Communications Engineering In this paper, a p-type channel TFT device with 6 terminals (4 gates, one drain and one source) has been proposed. The device has been constructed through Sentaurus TCAD device editor. Simple logic gates (NOR, NAND, NOT and XOR) are built by using different input configurations applied to four gates of the device. Device simulations have revealed that all gates can operate at 5 V with full functionality. The average ratio of the on-state current to off-state current is shown to be around 1000 which is good enough for simple applications in the large-area digital electronics systems. 16:40 Inverting versus Non-Inverting Dynamic Logic for Two-Phase Latch-free Nanopipelines Hector J. Quintero, Manuel Jiménez, María J. Avedillo and Juan Núñez. IMSE-CNM Very fine grained latch-free pipelines are successfully used in critical parts of high performance systems. These approaches are based in Domino logic and multi-phase clock schemes. Reducing the number of logic levels per clock phase and the number of phases to the minimum is a potential way to push the limits of speed. However the implementation of such architectures with just one logic level per clock phase and two clock phases is a challenge which requires extremely full-custom design and exhibits robustness concerns. In this paper we show that the non-inverting feature of Domino plays a critical role in these difficulties. We analyze and compare the performance of two-phase gate-level pipelines implemented with Domino and with ILP, an inverting dynamic gate we have proposed. Our experiments confirm that ILP pipelines are much more robust and could simplify design. 17:00 Memristive TaOx-based Median Filter Design for Image Processing Application Abubakr Sasi, Amirali Amirsoleimani, Majid Ahmadi and Arash Ahmadi. University of Windsor This work manifests the implementation of memristive 2-D median filter and extends previously published works on memristive filter design to include this emerging technology characteristics in image processing. The proposed circuit was designed based on Pt/TaOx/Ta redox-based device and Memristor Ratioed Logic (MRL). The proposed filter is designed in Cadence and the memristive median approved tested circuit is translated to Verilog-XL as a behavioral model. Different 512x512 pixels input images contain salt and pepper noise with various noise density ratios are applied to the proposed median filter and the design successfully has substantially removed the noise. In comparison with the conventional filters, it gives better Peak Signal to Noise Ratio (PSNR) and Mean Absolute Error (MAE) for different images with different noise density ratios while it saves more area as compared to CMOS-based design. 16:20-17:40 Machine learning and knowledge based design Room #115  Chair: Esteban Tlello-Cuautle, INAOE, Mexico 16:20 Tunable Floating-Point for Embedded Machine Learning Algorithms Implementation Marta Franceschi1, Alberto Nannarelli2 and Maurizio Valle1. 1University of Genoa, 2Technical University of Denmark, The development of embedded and real-time systems for Machine Learning data processing is challenging (e.g. IoT). Low latency, low power consumption and reduced hardware complexity should be the characteristics of such systems. Considering prosthetic applications which are error-tolerant, a technique that tunes the precision of operands and operations has been chosen for a Machine Learning algorithm used for tactile data processing. This paper presents the implementation of a Tunable Floating-Point (TFP) representation into a Singular-Value Decomposition (SVD) algorithm based on the One Sided Jacobi method. The TFP representations allowed high performance and efficiency improvements of the SVD algorithm. 16:40 Approximate fully connected neural network generation Tuba Ayhan and Mustafa Altun. Istanbul Technical University Approximate computing is exploited in implementation of fully connected networks for classification problems. A multiplier structure whose area is scalable over accuracy through approximate computing is proposed. In order to employ the multipliers in a network, an area reduction algorithm is formed. It can adjust the approximation level of multipliers while still maintaining the target classification performance, without prior information on the value of network weights. Implementing on a Spartan6 FPGA, up to 79% area saving is recorded for various performance targets. 17:00 Modelling Switched-Capacitor DC-DC Converters with Signal Transition Graphs Danhui Li, Delong Shang, Fei Xia and Alex Yakovlev. Newcastle University Switched Capacitor DC-DC converters play an important role in low power technologies such as energy harvesting systems as they can provide step-up voltage outputs with lower inputs. This paper models and analyses Switched Capacitor DC-DC converters with Signal Transition Graphs, which are originally used for modelling asynchronous circuits. With this new approach, the causality relations between phases, capacitors and internal signals in Switched-Capacitor DC-DC converter can be described distinctly, especially for some complicated converters. This is the first attempt at generating formal models for these types of components, which previously have been described by natural language and waveforms. 17:20 A Novel Multiple Membership Function Generator for Fuzzy Logic Systems Ramin Khayatzadeh and Mustafa Berke Yelten. Istanbul Technical University Electronics and Communications This paper presents a new multiple membership function generator which is capable of forming Gaussian, trapezoidal, triangular, S-shaped, and Z-shaped membership functions. To the best of authors’ knowledge, a single circuit that can concurrently generate Gaussian, trapezoidal, and triangular membership functions has not been reported in the literature yet. Proposed circuit is compatible with many fuzzy logic systems requiring different types of membership functions. The circuit is designed using a commercial 0.18 um CMOS technology and consumes a total power of 180 uW. The shapes of each membership function can be modified by properly chosen values of input and reference voltages. Functionality of all membership functions is validated across process corners with additional Monte Carlo analysis where temperature variations are considered, as well. 16:20-17:40 Reliability and Resiliency Atrium  Chair: Bernd Deutschmann, TU Graz, Austria 16:20 Increasing EM Robustness of Placement and Routing Solutions Based on Layout-Driven Discretization S. Bigalke1, T. Casper2, S. Schöps2, J. Lienig1 1TU Dresden, Germany; 2TU Darmstadt, Germany Nowadays, electromigration (EM) is mainly addressed in the verification step. This is no longer possible due to the ever increasing number of EM failures in the future. An EM-aware physical synthesis could reduce the number of critical locations but the layout complexities prevent this from already being used. To solve this problem, we propose a novel method to discretize placement and routing solutions to enable a fast EM analysis. In addition, we suggest adjustments in the placement and routing step to enhance the EM robustness based on early analysis results. In contrast to the standard approach of running a numerical simulation outside the physical design step and after the synthesis, we perform most of the analysis steps within our placement and routing tools to consider the results; thus enabling early and specialized EM-robust solutions. Particularly, our methodology exploits layout structures to enable an efficient discretization inside the geometrical representations of synthesis tools. We demonstrate how to reduce the discretization effort significantly while achieving sufficient accuracy to improve EM robustness. 16:40 Characterising Soft-Failures in Component-Level ESD Testing P. Schrey Graz University of Technology, Austria The gap between component-level and system-level Electrostatic Discharge (ESD) tests is an ongoing problem for microelectronics. Without powering the Device Under Test (DUT) during ESD tests, there is no way to detect problems during operation before the first prototype is available. Monitoring the response of selected pins of the DUT while stressing with Transmission Line Pulse (TLP) allows to detect soft-failure induced by TLP. Parameters used for soft-failure detection are included in the quasi-static Current over Voltage Characteristic. With this new characteristic, Integrated Circuit (IC) designers can provide information on DUT soft-failure susceptibility and ESD response to the system designers. Furthermore, a Wunsch-Bell-like characteristic for ESD induced soft-failure susceptibility is presented. 17:00 Torus Topology Based Fault-Tolerant Network-on-Chip Design with Flexible Spare Core Placement P. Veda Bhanu1, P. Kulkarni1, J. Soumya1, L. Cenkeramaddi2, H. Idsøe2 1BITS-PILANI Hyderabad, India; 1University of Agder, Norway The increase in the density of the IP cores being fabricated on a chip poses on-chip communication challenges and heat dissipation. To overcome these issues, Network-on-Chip (NoC) based communication architecture has been proposed as a viable solution. In the nanoscale era, NoCs are prone to faults which results in performance degradation and unreliability. Hence efficient fault-tolerant methods are required to make the system reliable in contrast to diverse component failures. With this background, the paper presents a flexible spare core placement in torus topology based fault-tolerant NoC design. The spare core position is chosen from the available positions in the torus network to care of the communications associated with the failed core. This paper proposes a meta-heuristic based Particle Swarm Optimization (PSO) technique to find a suitable position for the spare core that minimizes the communication cost. We have experimented with several application benchmarks reported in the literature by varying the network size and by varying the fault-percentage in the network. The results show a significant reduction in terms of communication cost compared to other approaches reported in the literature. 17:20 Design and Analysis of Energy-Efficient Self-Correcting Latches Considering Metastability C. Indra Kumar, A. Bulusu Indian Institute of Technology Roorkee, India In modern CMOS technologies, meta-stability is becoming an important issue for designing sequential systems, especially in the near/sub-threshold regime. This is because, with a reduction in supply voltage, mean time between failures (MTBF) increases exponentially. This paper presents a detailed analysis of the meta-stability in design of near/sub-threshold resilient flip-flops. We show that a proper transistor sizing, a selection of optimum number of fingers in the main path inverter of the slave stage, and an insertion of a small sized inverter in the output stage of the resilient flip flops can result a significant reduction in the resolution constant (œÑ). The post-layout simulation results show that the meta-stability-power-delayproduct (MPDP) improves using the modification as compared to an equivalent conventional design. This improves the resilient flip-flop‚Äôs resolution constant while incurring a design trade-off between power dissipation and performance. WEDNESDAY, July 4th 10:20-12:00 Modeling Room #103  Chair: Mustafa Berke Yelten, Istanbul Technical University Electronics and Communications Engineering, Turkey 10:20 Parameter Extraction Method Using Hybrid Artificial Bee Colony Algorithm for an OFET Compact Model Nihat Akkan1, Mustafa Altun2 and Herman Sedef1. 1 Yildiz Technical University, 2Istanbul Technical University Research on organic field effect transistors (OFETs) have been dramatically increased in the last decade, considering their lightweight and flexible structure as well as their practical and low-cost production. Building compact models and parameter extraction methods have also a critical importance in extensively using OFETs in electronic systems. In this paper, we propose a hybrid artificial bee colony algorithm as a parameter extraction tool and we compare it with purely mathematical and genetic algorithm-based parameter extraction methods. We apply these methods to a well-known OFET compact model for two different transistors, both having pentacene as organic semiconductor. We fabricated one of them (T2) in our laboratory and the other transistor (T1) is available in literature. The proposed approach shows a good agreement with the experimental data of T1 with normalized RMS error (NRMSE) of 0.26%. However, it is 8.29% for T2 due to limited measuremets. If the shape of the data were same, the parameter extraction approaches would be expected to perform more successfully for both OFETs as well. Results are tabulated and performances of the methods are compared in the paper. 10:40 Compact Drain Current Model of Nanoscale FinFET Considering Short Channel Effect in Ballistic Transport Regime Min Soo Bae, Chuntaek Park and Ilgu Yun. Yonsei University In this paper, the compact drain current model of 15-nm FinFET is proposed in ballistic transport regime. Based on the Lundstrom’s ballistic transport model, the proposed model is formulated for the improvement in both subthreshold and inversion region with channel length variation, including short channel effects and channel length modulation. The model can also capture the degeneracy of electrons using the empirical injection velocity. The proposed model is implemented in BSIM-CMG 108.0 and verified using the commercial TCAD modeling and simulation with the channel length variation. 11:00 Three-dimensional modeling of insulin pen for multi-electrode capacitive sensing Maria-Alexandra Paun and Catherine Dehollain. Swiss Federal Institute of Technology (EPFL) This work is devoted to the three-dimensional modeling and evaluation of multi-electrode capacitive sensing, in an insulin pen used by diabetic persons, for insulin dose precise detection. To this purpose a fully parameterized model has been developed in ANSYS for the insulin pen containing a smart cap which hosts the electrodes, used for the capacitive measurement and therefore dose detection. Different electrode configurations have been evaluated, including 3, 4, 6 and 8 electrodes. The numerical values of the electrode capacitances have been extracted using Maxwell 3D for all the configurations proposed. 11:20 Behavorial Switching Loss Modeling of Inverter Modules Kateryna Stoyka, Ricieri Akihito Pessinatti Ohashi and Nicola Femia. DIEM - University of Salerno This paper presents a new behavioral model for switching power loss evaluation in phase-shifted full-bridge inverter Power Modules (PoMs). The proposed model has been identified by means of a Genetic Programming (GP) algorithm combined with a Multi-Objective Optimization (MOO) technique. A large set of loss data, evaluated by means of analytical loss formulas, has been considered for the identification of a compact behavioral model. The GP-MOO approach considers the inverter switching frequency, input voltage, duty-cycle and load resistance as model input variables, and the MOSFET gate driver voltage and resistance as parameters influencing the coefficients values of the identified loss formula. The behavioral model loss predictions confirm their reliability for a wide range of operating conditions. 11:40 Modeling and Simulation of Digital Phase-Locked Loop in Simulink Nina Parkalian, Markus Robens, Christian Grewing, Volker Christ, Daniel Liebau, Pavithra Muralidharan, Dennis Nielinger, Ugur Yegin, Andre Zambanini and Stefan van Waasen Juelich Forschungszentrum This paper presents a high-level model for a digital phase-locked loop implemented in Simulink. This modeling enables the flexible and fast estimation of the design behavior and parameters before transistor-level implementation. The design includes a digital controlled oscillator that is defined using a linear s-domain model. Furthermore, the design of a time-to-digital converter based on oversampling and noise shaping is introduced to increase the effective resolution of the block. The simulation results of locking process, stability and phase noise verify the functionality of the model. 10:20-12:00 Circuit Synthesis Room #10  Chair: Elisenda Roca, University of Seville, Spain 10:20 Design Space Exploration of CMOS Cross-Coupled LC Oscillators via RF Circuit Synthesis Engin Afacan1 and Gunhan Dundar2. 1Kocaeli University, 2Bogazici University This study presents a parasitic-aware multi-objective RF circuit synthesis tool and performance space exploration of MOS cross-coupled LC oscillators using the developed tool. The developed tool utilizes SPEA-2 algorithm as a search engine, in which sophisticated sub-circuit models for passive devices are included; thus, the effect of layout-induced parasitics are considered during the optimization and the discrepancy between the circuit level and the layout level is minimized. As the case study, performance spaces of three different CMOS cross-coupled oscillators (NMOS, PMOS, and CMOS) are explored and compared by extracting Pareto-optimal fronts using the developed tool. Moreover, a further analysis is performed to demonstrate the effect of noise shaping capacitor on the oscillator performance. 10:40 Design and Optimization of a Class-C/D VCO for Ultra-Low-Power IoT and Cellular Applications Ricardo Martins1, Nuno Lourenço1, Nuno Horta1, Jun Yin2, Pui-In Mak2 and Rui Martins2. 1Instituto de Telecomunicações - Instituto Superior Técnico, University of Lisbon, 2State-Key Laboratory of Analog and Mixed-Signal VLSI and FST-ECE, University of Macau, Macao, China The proper analysis of design tradeoffs of Voltage-controlled oscillators (VCOs) embedded in state-of-the-art multi-standard transceivers is tedious and impractical, as a large amount of conflicting performance figures obtained from multiple modes, test benches and/or analysis must be considered simultaneously. In this paper, the performance boundaries of a complex dual-mode class-C/D VCO are extended using a framework for automatic sizing of radio-frequency (RF) integrated circuit (IC) blocks, where an all-inclusive test bench formulation enhanced with a measurement processing system enables the optimization of “everything-at-once” towards its true optimal tradeoffs. The dual-mode design and optimization conducted provided 512 design solutions with figures-of-merit above 192 dBc/Hz, pushing this topology to its performance limits on a 65 nm technology, by reducing 24% of the power consumption of the original design, while also showing its potential for ultra-low power, with more than 94% reduction. 11:00 On the Exploration of Promising Analog IC Designs via Artificial Neural Networks Nuno Lourenço, João Rosa, Ricardo Miguel Martins, Helena Aidos, Ricardo Póvoa, António Canelas and Nuno Horta. Instituto de Telecomunicações, Instituto Superior Técnico, Universidade de Lisboa In this paper, deep learning and artificial neural networks (ANNs) are used to size analog integrated circuits. In classical optimization-based sizing strategies the computational intelligent techniques are used to iterate over the map from devices sizes to circuits’ performances, provided by design equations or circuit simulations, whereas here, it is performed an exploratory work on how ANNs can be capable of solving analog integrated circuit sizing as a direct map from specifications to the sizing. The proposed methodology was implemented and tested on a real circuit topology, with promising results. Moreover, trained ANNs were able to extend the circuit performance boundaries outside the train/validation set, showing that more than a mapping for the training data, the model is capable of learning reusable design patterns and provide promising designs. 11:20 Expected Improvement-Based Optimization Approach for the Optimal Sizing of a CMOS Operational Transconductance Amplifier Nawel Drira1, 2, Mouna Kotti3, 4, Mourad Fakhfakh3, Patrick Siarry2 and Esteban Tlelo-Cuautle5. 1University of Gabès, Tunisia, 2University of Paris-Est Créteil, France, 3University of Sfax, 4Tunisia and University of Sousse, Tunisia and 5INAOE In this paper we consider the use of a new Kriging metamodeling technique for the efficient global optimization of analog circuits. It is based on the use of the so-called expected improvement criterion for the enhancement of the considered performance model. The efficiency of this approach, regarding to accuracy and computation time, is showcased via an example of the optimal sizing of a CMOS operational transconductance amplifier. A comparative study with performances of the conventional in-loop sizing technique, where the particle swarm optimization metaheuristic is used as the core of the optimization kernel, is presented. 11:40 Linearizing the Transconductance of an OTA Through the Optimal Sizing by Applying NSGA-II Luis Gerardo De La Fraga1 and Esteban Tlelo-Cuautle2. 1Cinvestav. Computer Science Department, 2INAOE, Department of Electronics The operational transconductance amplifier (OTA) can be linearized by adding circuit elements as in the source degeneration technique. In this work, we linearize the transconductance of a CMOS OTA by just sizing the MOS transistors and by applying the multi-objective algorithm known as non-dominated sorting genetic algorithm (NSGA-II). The OTA under optimization has a cascode stage and complementary input, and three objectives are chosen: linear transconductance, gain and bandwidth. The sizing is performed by using a CMOS integrated circuit technology of 180 nm. The feasible solutions provided by NSGA-II are presented and compared by selecting 2 and 3 objectives, and at the end, we show the time response of the linearized OTA by implementing a multi-phase sinusoidal oscillator. 10:20-12:00 Radio Frequency Circuits and Systems I Room #115  Chair: Catherine Dehollain, EPFL, Switzerland 10:20 A 4W 37.5-42.5 GHz Power Amplifier MMIC in GaN on Si Technology F. Costanzo, R. Giofrè, A. Salvucci, G. Polli, E. Limiti University of Roma Tor Vergata, Italy The design of a Q-band high power amplifier (HPA) in Microwave Monolithic Integrated Circuit (MMIC) technology is presented. The HPA is fabricated in a 100nm gate length Gallium Nitride on Silicon (GaN-Si) technology. The HPA, based on a four-stage architecture, was designed accounting for the de-rating rules foreseen for spatial use and to work in continuous wave (CW) conditions. Nevertheless, the realized HPA can provide a saturated output power larger than 36.5dBm with a gain and a power added efficiency higher than 22dB and 30%, respectively, in the operative band from 37.5GHz to 42.5GHz. The chip area is 3.54 x 3.5 mm2. Such results are in line with others state-of-art HPAs realized in more expensive GaN processes based on Silicon Carbide, thus demonstrating that high resistivity Silicon substrate can be efficiently adopted also in such a peculiar application. 10:40 An Integrated Power Detector for a 5GHz RF PA V. Qunaj, U. Celik, P. Reynaert KU Leuven, Belgium A fully integrated power detector is presented that detects both instantaneous RF voltage and current. Both signals are multiplied using an on-chip low-noise, high linearity mixer to measure the real power delivered to the load of an integrated PA operating at 5GHz in predictive 45nm CMOS technology. The dynamic range of the detector is 23.72dB with an accuracy of < ¬±0.5dB. Even under antenna load mismatch the detector is able measure the real power delivered to the load up to a voltage standing wave ration of 2.7:1 with an error < ¬±0.6dB. The power detector has no effect on the PA performance and can be integrated under the large output matching transformer, resulting in a cost efficient design. 11:00 Design of an E-band Doherty Power amplifier M. Najmussadat1, R. Ahamed1, D. Parveg2, M. Varonen2, K. Halonen1 1Aalto University, Finland; 2VTT Technical Research Centre of Finland, Finland This paper demonstrates the design of an E-band Dohrty power amplifier (PA) based in an 0.13 m SiGe BiCMOS technology. This design includes main and auxiliary amplifiers, lange coupler and a pre-amplifier. The designed power amplifier exhibits a saturated output power of 14.4 dBm and output referred P1dB of 11.7 dBm. The peak power added efficiency (PAE) of this amplifier is 19.2%. This PA shows PAE at P1dB of 17%. The PAE at 6-dB output power back off is 11.6%. The peak power gain of this Doherty PA is 23 dB at 75 GHz with a 3-dB bandwidth from 60 to 80 GHz. The designed Doherty PA consumes 52 mW of DC power and occupies an area of 900 um x 820 um excluding RF pads. 11:20 A Novel Multi-level CMOS Switching Mode Amplifier for Mobile Communication Signals R. Bieg, M. Schmidt, M. Grözing, M. Berroth University of Stuttgart, Germany This paper presents simulation results of a CMOS switching mode power amplifier (SA) in a 65nm technology with adjustable output voltage swing. The output stage is built in a stacked design to prevent dielectric breakdown of the transistors. Inverters at the top and bottom of the stack provide the supply voltage for the stack. The configuration offers a variable output voltage swing between one, two or three times the nominal transistor supply voltage. This paper demonstrates the advantages over a power amplifier with fixed output levels for signals with high peak to average output power ratio (PAPR). 11:40 Down-converter solutions for 77-GHz automotive radar sensors in 28-nm FD-SOI CMOS technology C. Nocera1, A. Cavarra1, G. Papotto2, E. Ragonese1, G. Palmisano1 1University of Catania, Italy; 2STMicroelectronics, Italy This paper presents a review of 77-GHz down-converter solutions for automotive radar sensors in 28-nm FD-SOI CMOS technology. A comparison of two different topologies based on common source (CS) and common gate (CG) stages is reported. The comparison is carried out at a power supply as low as 1-V and at 15-mA current consumption. CS-based and CG-based down-converters achieve a conversion gain of 27.5 and 21.3 dB over a ‚àí3-dB bandwidth of 16 GHz and 22 GHz, respectively, while exhibiting a noise figure of 7.8 dB and 9.1 dB. 10:20-12:00 Analog Circuits II Atrium  Chair: Marco Cerchi, ams Italy srl, Italy 10:20 Ultra Low Frequency Low Power CMOS Oscillators for MPPT and Switch Mode Power Supplies F. Galea, O. Casha, I. Grech, E. Gatt, J. Micallef University of Malta, Malta This paper presents the design of two low power consumption analog oscillators implemented in a 0.35¬µm CMOS technology. These oscillators were designed for a power conditioning circuit with an analogue Perturbation and Observation Maximum Power Point Tracker (MPPT) to maximize the scavenged power generated by energy harvesting devices. The nominal frequency of the two oscillators is 15Hz and 200kHz, respectively. The 15 Hz oscillator is used to clock the MPPT, whereas the second oscillator generates a sawtooth wave required for the pulse width modulation of the switch mode converter. Both oscillators work with a supply voltage of 1 V and use a reference current generated by a self-biasing zero temperature coefficient circuit. All the circuitry was designed to operate in the sub-threshold region in order to keep its power consumption to a minimum. The frequency of the 15Hz oscillator varies by 6.7% over a temperature variation from 0ºC to 80ºC. The total power consumption including the current reference circuit is 30nW at 27ºC and reaches a maximum of 90nW at 80ºC. The frequency of the 200 kHz oscillator varies by 19.6% over a temperature variation from 0ºC to 80ºC. The sawtooth generator, together with the current reference circuit, consume 63nW across this temperature range. 10:40 Analysis of Gain and Bandwidth Limitations of Operational Amplifiers in Sigma-Delta Modulators T. Saalfeld, A. Meyer, E. Schulte Bocholt, R. Wunderlich, S. Heinen RWTH Aachen University, Germany In Sigma-Delta modulator system design the loop filter coefficients are calculated based on ideal circuit behaviour. Advancing to an actual circuit implementation based on opera- tional amplifiers, which show finite gain bandwidth products, a deviation of these coefficients is observed. These influences which were not considered during initial coefficient development can lead to performance degradation or even instability. This paper presents an analysis of the influence of the 3 dB bandwidth and the DC gain of an opamp to the signal and noise transfer function of a third order Sigma-Delta modulator. Based on a mathematical analysis of the filters transfer function the influences to a complex integrator and a Tow-Thomas biquad are discussed in order to give a target specification for an opamp circuit implementation. 11:00 Design of a Low-power Ultrasound Transceiver for Underwater Sensor Networks G. Berkol, P. Baltus, P. Harpe, E. Cantatore Eindhoven University of Technology, Netherlands This paper presents an ultrasound (US) transceiver including a transmitter and a receiver for underwater wireless sensor nodes, where low-power operation is desired to extend the life-time of the network. A system-level analysis of the underwater communication has been performed by taking into account the underwater propagation and the medium characteristics to show their impact on the overall performance. In addition, a low-noise amplifier using an inverter-based topology has been introduced to ensure power efficiency of the receiver, where a bulk-feedback method is proposed to stabilize the output bias point of the inverter. Simulation results show that the proposed transceiver has a scalable power consumption from 1.95${\mu}W$ to 10.4${\mu}W$ while achieving 100${\mu}V$ to 20${\mu}V$ sensitivity at a $10^{-3}$ BER level. 11:20 On the Design of a Linear Delay Element for the Triggering Module at CERN LHC J. Gauci1, E. Gatt1, O. Casha1, G. De Cataldo2, I. Grech1, J. Micallef1 1University of Malta, Malta; 2INFN Bari, Italy This paper presents an analytical model of a linear delay element circuit to be employed in the triggering module for the High Momentum Particle Identification Detector (HMPID) at the CERN Large Hadron Collider (LHC). The aim of the analytical model is to facilitate the design of the linear delay element circuit, while maximizing its linearity and delay range. The analytical model avoids the need of time consuming parametric sweeps on the aspect ratios of the various transistors of the delay element in order to optimize it. In addition, the analytical model can be used to predict the variation of the delay with the input tuning voltage. The proposed analytical model is verified via the simulation of the delay element circuit using the 0.18 Œºm XFAB technology. 14:00-16:00 SMACD EDA Competition II Room #103  Chair: Ralf Sommer, IMMS GmbH, Germany & Engin Afacan, Kocaeli University, Turkey 14:00 Lithography Hotspots Detection Using Deep Learning Vadim Borisov and Jürgen Scheible. Reutlingen University The hotspot detection has received much attention in the recent years due to a substantial mismatch between lithography wavelength and semiconductor technology feature size. This mismatch causes diffraction when transferring the layout from design onto a silicon wafer. As a result, open or short circuits (i.e. lithography hotspots) are more likely to be produced. Additionally, increasing numbers of semiconductors devices on a wafer required more time for the lithography hotspot detection analysis. In this work, we propose a fast and accurate solution based on novel artificial neural network (ANN) architecture for precise lithography hotspot detection using a convolution neural network (CNN) adopting a state-of-the-art technique. The experimental results showed that the proposed model gained accuracy improvement over current state-of-the-art approaches. The final code has been made publicly available. 14:30 Impact Rating of Layout Parasitics in Mixed-Signal Circuits: Finding a Needle in a Haystack Georg Gläser, Martin Grabmann and Dirk Nuernbergk. Insitut für Mikroelektronik und Mechatronik Systeme gemeinnützige GmbH Parasitic couplings are the scourge of analog/mixed-signal (AMS) design sign-off. After the circuit has been verified, these layout-induced effects degrade the performance or even stability of the created system. In extreme cases, this may lead to malfunction under certain circumstances as for instance high-frequency electromagnetic interference (EMI). To verify the circuit by simulation, extraction is used to annotate the high number of parasitic elements to the circuit's netlist. Still, this tool does not point to a concrete coupling that causes the main impact on the performance. We propose an automated method to rate parasitic elements using a directed modification of the extracted post-layout netlist. By systematically removing parasitics and evaluating the performance, the designer is supplied with information about the main contributers to performance degradation. We demonstrate our approach by analysing and hardening an industrial voltage regulator layout with respect to EMI related influences. 15:00 ToPoliNano & MagCAD: a Complete Framework for Design and Simulation of Digital Circuits based on Emerging Technologies Umberto Garlando, Fabrizio Riente, Deborah Vergallo, Mariagrazia Graziano and Maurizio Zamboni. Politecnico di Torino Evaluating the performance of beyond CMOS devices poses many challenges to the research community. Several works analyze emerging technologies at device level; nonetheless an architectural design space exploration is fundamental to understand their potential. We present a design framework for emerging technologies, consisting of two tools ToPoliNano and MagCAD. It provides a top-down design flow and a methodology enabling the architectural exploration of emerging devices. 15:30 ReSeMBleD- Methods for Response Surface Model Behavioral Description Maike Taddiken, Steffen Paul and Dagmar Peters-Drolshagen. University of Bremen In this paper, a method for the generation of Response Surface Models for behavioral modeling is presented. To enable and automate this method, a MATLAB application supporting the complete modeling process has been developed. This includes initial model selection and validation, sensitivity analysis, automated simulation of sample and test points as well as regression model calculation. The tool is specialized for modeling the behavior of integrated circuit components, but can be used for other purposes as well. Additionally, the tool offers methods for the analysis and modeling of statistical data and can be easily extended by further functionalities. The application of the method is shown using an amplifier. 14:00-16:00 Digital Circuits and Sub-Systems Room #10  Chair: Jan Kovalsky, S3 Semiconductors, Czech Republic 14:00 A Novel Very Low Voltage Topology to implement MCML XOR Gates D. Bellizia1, G. Palumbo2, G. Scotti1, A. Trifiletti1 1University of Roma La Sapienza, Italy; 2University of Catania, Italy A new very low-voltage topology to implement MOS current mode logic (MCML) XOR gates is proposed in this paper. Instead of stacking several level of transistors to implement a two inputs XOR gate, a p-type differential pair is used to steer the current in n-type differential pairs through current mirrors. The proposed topology allows to reduce the minimum supply voltage of MCML XOR gates while guaranteeing a fully current mode behavior as in the conventional XOR gate. The proposed topology has been compared against the conventional and triple tail MCML XOR gates. Simulation results referring to a 40nm CMOS technology for VDD=1V confirm that the proposed folded circuit outperforms the triple tail MCLM XOR gate in terms of propagation delay. Furthermore both theoretical analysis and simulation results in a 40nm process show that the proposed topology is able to work with a VDD as low as 0.65V whereas state of the art topologies are not usable below 0.8V. 14:20 VLSI Design of Frequent Items Counting Using Binary Decoders Applied to 8-bit per Item Case-study K. Inoue1, T. Hoang2, X. Nguyen2, H. Nguyen2, C. Pham2 1Advanced Original Technologies, Japan; 2University of Electro-Communications, Japan In this paper, the Very-Large-Scale Integration design of Frequent Items Counting (FIC) is proposed. The fundamental idea is to use binary decoders to generate a matrix of binary values of all input items, with each column represents for one item‚Äôs binary value. Then, the sums are executed on the rows of the matrix to retrieve the input items‚Äô counting results. The proposed design is applied to the case-study of 8-bit/item. That means 256 different types of items in total. For storing the counting results, various options of count-register are also presented. The proposed architecture is implemented with seven option of count-register from 8-bit counter to 32-bit counters, with the incremental of 4-bit at a time. The design was implemented on the Altera Arria V SoC Development Kit. After successful built and verified on Field Programmable Gate Array (FPGA), the design was synthesized using Synopsys tools with the process of SOTB (Silicon on Thin Buried-oxide) 65nm. The FPGA results achieved the average speed of 3,883.1 and 4,638.62 million item-counting per second for the 32-bit and 8-bit count-register options, respectively. Compared to our previous work and the software-based application, the achieved speed results are more than three times and more than 150 times faster, respectively. The SOTB-65nm builds achieved the theory speed about 75% of the average practical results of FPGA implementations. 14:40 Multi-Stage Complex Notch Filtering for Interference Detection and Migitation to Improve the Acquisition Performance of GPS S. Arif, A. Coskun, I. Kale University of Westminster, United Kingdom Continuous Wave Interferences (CWIs) can degrade the accuracy of a Global Positioning System (GPS) receiver and moreover it can completely deteriorate receiver‚Äôs normal operation. In this paper a low-cost anti-jamming system design is presented for the mitigation and detection of CWIs for GPS receivers. The anti-jamming system comprises of parameterizable Complex Adaptive Notch Filter (CANF) module which is able to detect and excise single or multiple CWIs. The CANF module is composed of a first , second and third order infinite-impulse response filter with an Auto-Regressive Moving Averager structure. The proposed CANF detects the existence of the CWI and estimates JNR level of incoming signal by using the statistical value of the adaptive parameter b_0. The impact of the CANF module on the acquisition is analyzed. Moreover, a simple and innovative system level model is proposed which can utilize each CANF efficiently with threshold setting of JNR estimation within the adaptation block. Threshold setting parameters provide trade-off between effective excision of CWI, order of the filter and power consumption. This results in a parameterizable CANF module and provide effective for the mitigation of interferences with a high-power profile for GPS based applications. 15:00 Stall-Aware Fixed-Point Implementation of LMS Filters D. Esposito, G. Di Meo, D. De Caro, E. Napoli, N. Petra, A. Strollo University of Napoli Federico II, Italy Least-Mean-Square (LMS) is the most popular adaptive filtering algorithm, due to its numerical stability, satisfactory steady-state error and relatively low computational complexity. LMS algorithm is commonly employed in a multitude of tasks such as channel equalization, adaptive noise cancellation, system identification and frequency tracking. Owing to its computational complexity, LMS algorithm is commonly implemented in hardware, in which, due to speed and energy constraints, a fixed-point arithmetic is usually adopted. As shown in the literature, the effects due to fixed-point arithmetic alter the behavior of the algorithm, causing a significant increase in the steady-state error, due to the so-called stall phenomenon. In this paper we propose a novel fixed-point scheme which significantly limits the stalling. This gives increased flexibility to the designer in the choice of the step-size, that controls the tradeoff between convergence rate and steady-state-error. Implementation results in a 40nm CMOS technology are presented in the paper, to assess the impact of the proposed scheme in terms of area, speed and power. 15:20 A SpaceFibre multi lane codec System on a Chip: enabling technology for low cost satellite EGSE P. Nannipieri1, G. Dinelli1, D. Davalle2, L. Fanucci1 1University of Pisa, Italy; 2IngeniArs, Italy In the last few years, data rate requirement on onboard satellite communication systems significantly grown. The need of high speed networks led to the birth of the SpaceFibre protocol, which is able to run at several Gigabit per second and operates over both optical fibre and copper cables. A key feature of SpaceFibre is the possibility to have multi lane link, which increases the overall achievable data rate and link reliability. The growing complexity of satellite payload communication systems requires the definition an accurate monitoring and testing system. In this paper a multi lane SpaceFibre interface integrated in a System on a Chip is presented as enabling technology for an electrical ground segment equipment. 15:40 Design and implementation of a complete test equipment solution for SpaceWire links A. Marino, L. Dello Sterpaio, L. Fanucci University of Pisa, Italy Spacecraft used in space mission have on-board a large number of peripherals such as instruments, mass-memory, downlink telemetry, sensors, actuators and processors. The State-Of-The-Art for the on-board spacecraft communication is the SpaceWire standard, which connects on-board devices directly, via point-to-point communication, or indirectly via router or switch. This paper presents the architectural design and the implementation of a complete test equipment solution for SpaceWire link. This is designed in order to have in a single device the possibility to emulate both a single SpaceWire device and a portion of a SpaceWire network. A system demonstrator was implemented to validate the equipment features. 14:00-16:00 Radio Frequency Circuits and Systems II Room #115  Chair: Dalibor Biolek, University of Defence Brno, Czech Republic 14:00 A Novel Hybrid Polar-I/Q Modulation Method relaxing RF Phase Modulator Design Requirements T. Buckel1, P. Preyler1, E. Hager1, T. Mayer1, S. Tertinek1, A. Springer2, R. Weigel3 1Intel, Austria; 2University of Linz, Austria; 3University of Erlangen-Nuremberg, Austria A novel modulation scheme enabling a seamless transition between digital-intensive quadrature and polar transmitter architectures by combining inphase / quadrature (I/Q) with phase modulation is presented. By incorporating phase modulation the quadrature RF digital-to-analog converter (DAC) input codewords peak to average power ratio is reduced. Therefore, the quadrature RF-DAC can be operated in a lower back-off region resulting in higher average output power and efficiency. Simulation results for LTE uplink transmission including the novel modulation scheme in combination with a power efficiency model for a shared-cell, switched-capacitor RF-DAC are shown. Compared to a digital-quadrature transmitter the average output power and efficiency can be increased, approaching the digitalpolar limit while showing significantly lower tuning-range requirements on the phase modulation path. 14:20 A Sub-1V, 72 μW Stacked LNA-VCO for Wireless Sensor Network Applications E. Kargaran, D. Manstretta, R. Castello University of Pavia, Italy Reducing the power consumption of RF transceivers is the main goal to meet the requirements of wireless sensor network (WSN) and Internet-of-Things (IoT) applications. An ultra-low power combined LNA-VCO is presented in this work with RF performance beyond the requirements of the intended application. The LNA power is reduced by factor of 12 in contrast to a single common-gate transistor using the same current to achieve impedance matching to 50 ÔÅó thanks to passive gain boosting and current reuse. Furthermore, to improve the voltage efficiency, the VCO is stacked on the top of LNA. Simulated in 40 nm CMOS technology, the combined LNA-VCO consumes only 72 ŒºW from 0.9 V supply voltage. At 2.4 GHz, LNA shows NF and voltage gain of 3.1 dB and 23 dB, respectively, while the VCO operates at 4.8 GHz and has a phase noise of -105.8 dBc/Hz at 1 MHz offset frequency, corresponding to a FoM of 194.1 dBc/Hz. 14:40 Low Power Locking Detector for Frequency Calibration of Multi-Frequency Injection Locked Oscillators A. Boulmirat, C. Jany, A. Siligaris, J. Gonzalez Jimenez CEA-TECH, France This paper presents a locking detector used as a first stage in the frequency calibration techniques for Multi-Frequency Injection Locked Oscillators (MFILO). It provides a high detection level and relaxes design constraints on the calibration circuit that follows. This technique will allow lower levels of power consumption with smaller occupied area for the frequency calibration circuits. 15:00 A novel true logarithmic amplifer in 0.25 µm GaN on SiC technology for radar applications A. Salvucci, M. Vittori, S. Colangeli, G. Polli, E. Limiti University of Roma Tor Vergata, Italy A new circuit topology for a true logarithmic amplifier (TLA) basic cell is presented. The basic cell is synthesized in quasi-distributed form as the cascade of two single-FET stages. Whereas the operating principle of the overall TLA is well-known (i.e., cascading several hard-limiting cells), the topology of the proposed basic cell is not common. The broadband characteristics and the extreme compactness of the proposed architecture make it particularly suitable for the realization of multi-stage TLAs. The proposed basic cell is then adopted to design, as a test vehicle, a six-stages TLA, using a 0.25 ¬µm GaN-on-SiC HEMT technology provided by UMS foundry. The final MMIC exhibits a broadband behavior, in the range 1.2 GHz-2.2 GHz, with a global logarithmic error of ¬±1 dB over 60 dB of input dynamic range (IDR). 15:20 Ka-/V-band self-biased LNAs in 70 nm GaAs/InGaAs Technology G. Polli, M. Vittori, W. Ciccognani, S. Colangeli, F. Costanzo, A. Salvucci, E. Limiti University of Roma Tor Vergata, Italy In this paper, two LNAs, designed to operate in Ka and V bands, and realized in a 70 nm GaAs/InGaAs technology, are presented. Both amplifiers have a 2-stage structure featured by source feedback and self-biasing networks to improve noise performance and to simplify the external circuitry, respectively. Total area occupation of the realized MMICs is 3x1.2 mm2 and 3x1 mm2. The Ka-band amplifier exhibits a noise figure lower than 1.5 dB over 27-31.5 GHz and a gain between 16 dB and 18 dB. The V-band LNA has a 1.7 dB noise figure in the 47-51 GHz band, with an associated gain between 14.5 dB and 15.5 dB. 15:40 Single MMIC receivers for C-band T/R module in 0.25 µm GaN technology A. Salvucci, G. Polli, A. De Padova, S. Colangeli, F. Costanzo, W. Ciccognani, E. Limiti University of Roma Tor Vergata, Italy In this contribution two different versions of MMIC LNAs integrating the limiting function are presented. The chips are designed with 0.25 µm gate length GaN on SiC technology as provided by Leonardo foundry, and arrange the receiving circuitry of a T/R module operating in C-band, specific for AESA systems. The final performance show the differences of the two circuits, which were designed with different methodologies. For the first version the constant mismatch circles method was applied, while for the second version, the typical design method for LNAs was adopted. Both circuits use the same switch (absorptive SPST), that exhibits an isolation level better than 30 dB and insertion loss lower than 0.6 dB. The first version shows a wider operation bandwidth, with a noise figure of 2.2 dB, a gain of 35.5 dB, and excellent levels of return loss (22 dB for input and 23 dB for output). The second version exhibits a noise figure of 2.1 dB, a gain of 35.5 dB, with return losses of 22 dB and 20 dB for input and output respectively. 14:00-16:00 SS New Solutions for Analog and Radio-Frequency Layout Synthesis Atrium  Chair: Nuno Lourenço & Ricardo Martins, Instituto de Telecomunicações / Instituto Superior Técnico - Universidade de Lisboa, Portugal 14:00 Handling the Effects of Variability and Layout Parasitics in the Automatic Synthesis of LNAs F. Passos1, Ricardo Miguel Martins2, Nuno Lourenço2, Elisenda Roca1, Rafael Castro Lopez1, Ricardo Póvoa2, António Canelas2 and Nuno Horta2, Francisco V. Fernández1. 1IMSE-CNM, CSIC, 2Instituto de Telecomunicações, Instituto Superior Técnico – ULisbon, Universidade de Lisboa This paper exposes the problematic issue of not considering device variability and layout parasitic effects in optimization-based design of radiofrequency integrated circuits. Therefore, in order to handle these issues, a new design methodology that performs an all-inclusive optimization is proposed, by taking into account the process variability, and, performing the complete layout automatically while performing an accurate parasitic extraction during the optimization for each candidate solution. Furthermore, the problematic inductor parasitics are also taken into account with EM-accuracy, by using a state-of-the-art surrogate modelling technique. The methodology was applied in the design and optimization of a low-noise amplifier, obtaining a set of extremely robust designs ready for fabrication. 14:20 ABSYNTH: A Comprehensive Approach for Full Front to Back Analog Design Automation Abhaya Chandra Kammara and Andreas Koenig. TU Kaiserslautern, ISE Abstract—The benefits of any form of automation are well known, however unlike most other forms of automation, analog design automation (ADA) is not yet accepted by most designers as part of the work-flow. The goal of this work is to explore the needs and the targets to make ADA viable in industry and research. There are various approaches targeting different sets of designers of different experience levels. In this work, we present ABSYNTH, an ADA tool which can be used with or without expert knowledge depending on the interest and proficiency of the user. It also makes use of advanced modeling techniques like Support Vector Regression, and other neural network techniques for learning the circuit models during the initial runs and contribute during repeated runs of the circuit. Four circuits have been presented where automation of different steps have been carried out. three of these circuits have been used in a manufactured chip, that will soon be tested. A generic hybrid layout generator based on a constrained template which can be optimized while maintaining the matched structure has been presented. This improves the quality of the layout by producing results comparable or better than those predicted by simulators without parasitic extraction. 14:40 Spec-to-Layout Automation Flow for Buck Converters with Current-Mode Control in SOC Applications Hsin-Ju Hsu, Wan-Chun Chen, Long-Ching Yeh, Chien-Nan Jimmy Liu. National Central University, Taiwan This paper presents an integrated automatic design flow for DC-DC power converter circuits. This flow includes circuit synthesis, large and small signal circuit analysis, layout placement/routing, and post-layout simulation. In order to improve the transient response of DC-DC conversion, the buck converter with current-mode controller is chosen as the target of this flow. We apply both the equation-based and the simulation-based methods to improve the accuracy of circuit synthesis. And an advanced layout placement methodology suitable for mixed-mode and power circuits is adopted to optimize the on-chip area. As demonstrated through several cases, this flow is able to generate a feasible buck converter from specification to layout in a short time. 15:00 Classifying Analog and Digital Circuits with Machine Learning Techniques toward Mixed-Signal Design Automation Guan-Hong Liou, Shuo-Hui Wang, Yan-Yu Su and Mark Po-Hung Lin. National Chung Cheng University For modern IoT applications, one of the most challenging and time-consuming tasks is the layout design of the mixed-signal IC in an IoT device, which integrates both analog and digital circuits into a single chip. There is no industrial tool which can automatically identify analog and digital sub-circuits in a mixed-signal design to accelerate the layout design automation. In this paper, we first introduce a unique matrix representation to encode circuit netlists, and then apply machine learning algorithms to automatically classify/identify analog and digital sub-circuits. The experimental results show that the proposed method is promising based on the CNN algorithm. 15:20 Mismatch-aware Placement of Device Arrays using Genetic Optimization Islam Nashaat1, Inas Mohammed2, Mohamed Dessouky3 and Hazem Said4. 1Si-Vision Ltd., 2Mipex Ltd., 3Mentor Graphics Egypt, 4Faculty of Engineering, Ain Shams University This paper presents an automatic matched devices layout generation tool. An adapted form of genetic optimization is used to minimize the overall systematic mismatch due to oxide gradients and STI effect. A new STI evaluation methodology is introduced based on simulation and foundry models. The tool is capable of generating a current mirror or capacitor array layout pattern with optimal systematic mismatch, STI mismatch, and even both types of mismatch. 15:40 On Closing the Gap Between Pre-simulation and Post-simulation Results in Nanometer Analog Layouts Po-Cheng Pan1, Hung-Wen Huang1, Chien-Chia Huang1, Abhishek Patyal1, Hung-Ming Chen1 and Tsun-Yu Yang2. 1National Chiao Tung University, 2Taiwan Semiconductor Manufacturing Co., Ltd. In order to generate analog layout in advanced technology, it still remains lots of challenges due to the imprecise estimation of critical performance parameters. We propose an upgraded decision making framework, PEDefer, to decompose existing layout into decisive components for performance estimation. In this work, the objective is to synthesize layout solutions based on the performance estimation of user-defined constraints and existing templates. The constraints of the circuit are priorly tackled in the partition and layout enumeration stage. In addition, we attempt to have partial layout pieces as exchangeable blocks to perform pseudo-post-simulation This is to put simulation factors in the evaluation during layout enumeration strategy. The experiments show that this flow guarantees valid analog layout results whose performances are more close to netlist-level simulation than manual designed or migrated layouts with minimal overhead. THURSDAY, July 5th 10:20-12:00 Sensing and Biomedical Circuits I Room #103  Chair: Franco Maloberti, University of Pavia, Italy 10:20 Decreasing the Actuation Voltage in Electrowetting on Dielectric With Thin and Micro-Structured Dielectric S. Türk1, E. Verheyen1, R. Viga1, S. Allani2, A. Jupe2, H. Vogt2 1University of Duisburg-Essen, Germany; 2Fraunhofer IMS Duisburg, Germany This work presents the analysis of the minimum actuation voltage Vmin for droplet actuation with electrowetting on dielectric (EWOD). First, the fundamentals of electrowetting are described. In the second chapter, the impact on the actuation voltage in EWOD is shown by a dielectric deposited with atomic layer deposition (ALD) and micro-structured surface. In the last part, results of a simulation with COMSOL Multiphysics¬Æ are presented to verify the hypothesis and a short discussion about the results is given. 10:40 Exploiting nonlinearities to improve the linear region in an electrostatic MEMS demodulator J. Scerri, B. Portelli, I. Grech, E. Gatt, O. Casha University of Malta, Malta This paper presents a technique whereby the overall nonlinear behavior of an electrostatically actuated and sensed MEMS is linearised for most of its usable range. The nonlinear characteristics are first analysed theoretically. This analysis reveals that the nonlinearity can be ‚Äòneutralised‚Äô by replacing the spring with a nonlinear - cubic stiffness - spring. Finding a feasible solution requires finding a compromise between a large number of geometric dimensions and constraints; this was achieved by making extensive use of MATLAB‚Äôs optimization toolbox. The device having optimal dimensions was manufactured using the SOIMUMPs process and lab measurements confirmed that the overall nonlinearity was practically eliminated for actuation voltages of 4 volts and upwards. 11:00 Mutli-Channel Electrotactile Stimualtion System for Touch Substitution: A Case Study H. Fares1, L. Seminara1, H. Chible2, S. Dosen3, M. Valle1 1University of Genova, Italy; 2Lebanese University, Lebanon; 3Aalborg University, Denmark Reconstructing the sense of touch in prosthetics is a long-standing research challenge. To this aim, the prosthesis can be supplied with sensory arrays to measure the tactile interaction with the environment. In addition, a reliable feedback system is required to code and transmit the measured somatosensory information to the residual limb. This paper presents a multichannel electrotactile stimulation interface. Two coding schemes (mixed and uniform coding) were tested to assess the ability of the subject to localize the stimulation (identify the active pad). The outcome measures were position recognition and frequency discrimination. Our preliminary results show high accuracies in discriminating different frequency levels, i.e., 80% for low-level frequencies and 87% for high-level frequencies. In addition, the mixed coding has substantially improved the spatial localization. These are important insights regarding the development of multichannel sensing and stimulation systems for feedback in prosthetics. 11:20 Modeling of a capacitive sensor dedicated to drug injection S. Joly1, A. Lepple-Wienhues1, C. Dehollain2 1Valtronic Technologies, Switzerland; 2EPFL, Switzerland It is a quite complex task to monitor patients who inject insulin using injection pens. Due to the repetition of injections, and the numerous applicable parameters the patient can easily make mistakes. It is difficult for caretakers to follow these injections and to detect errors. In order to reduce this problem, a device which measures the volume of drug using electric fields has been developed. A theoretical model, simulations and experiments have been conducted to validate this measurement technique. The experiments confirm the theory and simulations results. A sensitivity around 5fF per 10¬µl has been found and a good repeatability between three caps has been achieved. The standard error equals 0.44fF (¬±4.12%) for 10¬µl of insulin injections. 11:40 Lock-In Based Differential Front-End for Raman Spectroscopy Applications A. Ragni, G. Ferrari, G. Sciortino, M. Sampietro, D. Polli, V. Kumar1, F. Crisafi Politecnico di Milano, Italy The intrinsic sensitivity limit of Stimulated Raman Spectroscopy (SRS) is given by the shot noise of the optical stimulation. However, it is seldom reached due to the electronic noise of the front-end amplifier and the intensity fluctuations of the laser source. Here, we present a low-noise differential amplifier able to compensate the common-mode fluctuations given by the laser and to reach a sensitivity better than 10 ppm thanks to the lock-in technique. 10:20-12:00 Automotive Circuits and Systems Room #10  Chair: Alberto Gola, ams Italy srl, Italy 10:20 Electric Vehicle Battery Management Sytem Using Power Line Communication Technique A. Pake1, W. Pribyl2, G. Hofer1 1Infineon Technologies, Austria; 2Graz University of Technology, Austria This paper presents the analysis and test of a power line communication system targeting the communication between each battery cell and the battery management system located in an electric vehicle. The battery type which is used for analysis and for the lab measurement is 18650 [1] and the objective is to use a stack of batteries as a channel to transmit and receive digital data with high data rate using FSK modulation with 10MHZ carrier frequency. 10:40 Evaluation of Frontend Readout Circuits for High Performance Automotive MEMS Accelerometers A. Lanniel1, T. Alpert1, T. Boeser1, M. Ortmanns2 1Bosch, Germany; 2University of Ulm, Germany This paper reviews and evaluates different capacitive sensor readout frontend circuits for high performance MEMS applications. Fully-differential, pseudo-differential, open-loop and single-ended architectures are analyzed. Furthermore, the primary design parameters and the tradeoffs are presented. The focus is placed on size, linearity, EMC robustness, noise considerations and sensitivity. This work analyses existent readout architectures and derives the best for automotive specifications. 11:00 Real Time Defect Detection of Wheel Bearing by Means of a Wirelessly Connected Microphone E. Raviola, F. Fiori Politecnico di Torino, Italy In this work, an electronic system aiming to automatically monitor the state of health of wheel bearings, is proposed. The focus is on designing a low cost, small size and wirelessly interfaced module. Acoustic emissions are exploited to detect defects by means of a low cost micro electro-mechanical system (MEMS) microphone. A microcontroller was used to evaluate the frequency spectrum and to interface the system through a wireless data link. The designed module successfully achieved the proposed goals. Finally, a novel measurement process is presented to evaluate the system performance under realistic conditions. 11:20 Multi object detection in direct Time-of-Flight measurements with SPADs J. Haase, M. Beer, J. Ruskowski, H. Vogt Fraunhofer IMS Duisburg, Germany We present several contributions of our test system to detect multiple targets with the direct time-of-flight technique. With a precise time-to-digital-converter it is possible to capture the time-of-flight of a short light pulse reflected by a target with high temporal resolution. Based on this technique we can relate the single events to its resulting distance and separate the different objects. 10:20-12:00 High Frequency Room #115  Chair: Mohamed Dessouky, Ain Shams University - Faculty of Engineering, Egypt 10:20 A 20 dB Gain Two-Stage Low-Noise Amplifier with High Yield for 5 GHz Applications António Canelas, Ricardo Póvoa, Ricardo Miguel Martins, Nuno Lourenço, Jorge Guilherme and Nuno Horta Universidade de Lisboa, Instituto de Telecomunicações, Instituto Superior Técnico – ULisbon This paper presents the design of a two-stage low-noise amplifier (LNA) in a standard 130 nm CMOS technology, operating around 5 GHz, and fully synthesized with an automatic yield-aware integrated circuit (IC) design flow. The topology described in this paper does not require external bias, and is composed of two common-source amplifying stages and a subsequent common-drain output buffer. Simulation results of a high yield solution achieved by AIDA-C, a state-of-the-art multi-objective circuit design tool, show that a forward gain of around 20 dB, with a noise figure around 2.25 dB and a 1.3 GHz bandwidth can be achieved with this topology, draining less than 7 mA from a 1 V voltage supply source. Finally, the results achieved in this work are compared with a set of previously published LNA topologies, proving the benefits of both the topology and the automatic IC design tool. 10:40 Analytical Method for Ultra-Low Power UWB Low-Noise Amplifiers Ahmed Elsayed1, Mostafa Abutaleb1, Mohamed Eladway1 and Hani Ragai2. 1Helwan University, 2Ain Shams University This paper presents a MOSFET model for ultra-low power radio-frequency integrated circuits (RFICs) design. In addition, we discussed the concept of the Operating Parameter (OP) as the main design parameter used to determine the operating point, from weak, via moderate, or strong inversion. The proposed OP based analytical model is applied to an LNA design (3-5 GHz) in 130 nm CMOS technology. Simulation results showed a minimum noise figure (NF) of 2.3 dB, max gain 9.6 dB and 0.25 mW power dissipation. The figure of merit (FoM) is found to be superior to previous design techniques. 11:00 Temperature performance of meander-type inductor in silicon technology Aleksandar Pajkanovic1 and Goran Stojanovic2. 1Faculty of Electrical Engineering, University of Banja Luka, 2Faculty of Technical Sciences, University of Novi Sad In this paper, an inductor of meander topology is designed using Cadence integrated circuit toolchain. The structure is fabricated using a 130 nm standard CMOS technology node. Characterization is performed at frequencies up to 35 GHz and at temperatures of 20ºC, 50ºC and 80ºC. For the experiment an RF probe station with a temperature controllable chuck has been used. The results this set-up yielded include inductance, Q-factor and parasitic resistance behavior versus temperature. Meander topology temperature performance is presented and discussed. 11:20 An universal model for milimeter-wave integrated transformers Johannes Hermann1, David Bierbuesse2 and Renato Negra2. 1RWTH Aachen University, 2Chair of High Frequency Electronics - RWTH Aachen University This work reports on an universal lumped element model for integrated millimeter-wave (mmWave) transformers which is valid up to 100 GHz. The presented 2-pi architecture covers the calculation of planar and stacked transformer topologies as well as higher winding ratios and different geometries. All model components depend both on the transformer dimensions and technological parameters. A verification by electromagnetic field simulations in a 65 nm CMOS process results in a close agreement to the calculated S-parameter set. 11:40 On the Sparsification of the Reluctance Matrix in RLCk Circuit Transient Analysis Charalampos Antoniadis, Nestor Evmorfopoulos and Georgios Stamoulis. Department of Electrical and Computer Engineering, University of Thessaly, Greece The ever increasing frequency scaling of contemporary very large scale integrated circuits has introduced the necessity to factor in signal integrity the analysis of inductive effects arising within the different blocks of an IC. The efficient simulation of the inductive effects requires sparsification of the dense inductance matrix, or its inverse (called reluctance matrix) which is diagonally dominant and more amenable to sparsification. However, direct truncation of matrix entries below a certain threshold introduces unacceptable error in transient analysis for the high sparsity ratios we are interested in. In this paper, we present a graph sparsification algorithm that preserves the eigenvalues of the reluctance matrix and results to sparse approximations that offer better and bounded accuracy in transient analysis. Experimental results indicate that sparsity ratios over 99% can be attained with a negligible error in transient analysis. 10:20-12:00 Simulation Atrium  Chair: Maria Cristina Piccirilli, Department of Information Engineering University of Florence, Italy 10:20 Efficient Hotspot Thermal Simulation via Low Rank Model Order Reduction George Floros, Nestor Evmorfopoulos and George Stamoulis. University of Thessaly Efficient full-chip thermal simulation is among the most challenging problems facing the EDA industry today, due to the need for solution of very large systems of equations that require unreasonably long computational times. However, in most cases, temperature is not required to be computed at every point of the IC but only at certain hotspots, in order to assess the circuits compliance with thermal specifications. This makes the thermal analysis problem amenable to Model Order Reduction (MOR) techniques. System-theoretic techniques like Balanced Truncation offer very reliable bounds for the approximation error, which can be used to control the order and accuracy of the reduced models during creation, at the expense of greater computational complexity to create them. In this paper, we propose a computationally efficient low-rank Balanced Truncation (BT) algorithm that retains all the systemtheoretic advantages in the reduction of model order for fast hotspot thermal simulation. Experimental results demonstrate a 39X order reduction and very tight accuracy bounds. 10:40 A Combinatorial Multigrid Preconditioned Iterative Method for Large Scale Circuit Simulation on GPUs Dimitrios Garyfallou, Nestor Evmorfopoulos and Georgios Stamoulis. University of Thessaly Efficient large scale circuit simulation is among the most challenging problems facing the EDA industry today, since it is the only feasible way to verify a circuit's behaviour prior to manufacturing. In recent years, the emphasis has been placed on preconditioning methods which reduce the number of iterations for solving large Symmetric Diagonally Dominant systems resulting after the Modified Nodal Analysis. This paper presents a GPU-accelerated Preconditioned Conjugate Gradient (PCG) iterative method preconditioned by the Combinatorial Multigrid (CMG) for fast DC and transient analysis of large-scale linear circuits. Experimental results on IBM industrial power grids demonstrate speedups up to 4.69x and 4.50x for the PCG method and the CMG preconditioning algorithm, respectively, over the optimized CPU implementations. 11:00 Statistical Simulations of Delay Propagation in Large Scale Circuits Using Graph Traversal and Kernel Function Decomposition Jennifer Freeley, Dmytro Mishagli, Tom Brazil and Elena Blokhina University College Dublin In this paper we propose a new methodology to determine the delay of combinational circuits within the framework of statistical static timing analysis (SSTA). A new algorithm for the traversing of the timing graph is created. Assuming initial delays of the input signals and operation time of gates to be normally distributed, the exact analytical solution for a non-Gaussian probability density functions (PDF) of the resulting delay is obtained. Then, the approximation of a non-Gaussian PDF by a linear combination of kernel functions is proposed. This allowed us to build a novel closed-loop algorithm for the calculation of delay propagation in combinational circuits. Possible extensions and future steps are discussed. 11:20 LUT-based Stochastic Modeling for Non-Normal Performance Distributions Maike Taddiken, Theodor Hillebrand, Steffen Paul and Dagmar Peters-Drolshagen. University of Bremen Process variations have a large influence on the behavior of integrated circuits. Although individual process parameters are mostly considered normal or uniformly distributed, the resulting performance distribution of a circuit cannot always be assumed to be normally distributed due to non-linearities. In this paper an approach is presented which uses Kernel Density Estimation to calculate the non-normal performance distributions. The resulting probability density function is approximated by means of curve fitting with a Gaussian model to reduce complexity. A Look-Up table based stochastic model is build by analyzing the performance distribution at different operating conditions. In order to draw random samples from the distribution, slice sampling is applied. The modeling is shown at the example of an amplifier. 11:40 Advanced Modeling Methodology for expedient RF SoC Verification and Performance Estimation Fabian Speicher, Jonas Meier, Christoph Beyerstedt, Ralf Wunderlich and Stefan Heinen. RWTH Aachen University While the complexity of modern RF systems on chip grows significantly, the methods for functional verification can not hold pace. Powerful tools, that are available for the verification of purely digital systems are missing for analog/mixed-signal systems. This paper proposes a method to improve the capabilities of a high level programming language to verify an AMS system design covering RF performance issues. This is done in Cadence using SystemVerilog HDL and a direct programming interface to C++. As an example, a signal representation and signal processing in the spectral domain to handle the issues of nonlinear frequency conversion is presented. 14:00-16:00 SS Modeling, design and control of power converters with non linear passive power components Room #103  Chair: Giulia di Capua & Nicola Femia, University of Salerno, Italy, Marco Storace, University of Genoa - DITEN, Italy 14:00 Fast converter simulation method including parasitic nonlinear capacitances Eva Schmidt and Thomas Duerbaum. Friedrich-Alexander University of Erlangen-Nuremberg Converter topologies of SMPS, for example in consumer products, have to fulfill many specifications and demands especially in matters of efficiency and low overall costs. In order to optimize these converters, simulation methods have to be found that predict their real behavior accurately within short simulation time. However, simulation accuracy often suffers from neglection of nonlinear component characteristics, especially nonlinear capacitances associated with semiconductor devices. Integrating them in Sample Data Modeling generates a simulation method that achieves both goals, short simulation durations and results close to reality. 14:20 Pulse Compression for Ferrite Inductors Modeling in Moderate Saturation Pietro Burrascano1, Giulia Di Capua2, Nicola Femia2, Stefano Laureti1 and Marco Ricci3. 1University of Perugia, 2University of Salerno, 3University of Calabria A reliable analysis of Ferrite Core (FC) inductors operating with moderate saturation is a fundamental requirement in the design of high-power-density switch-mode power supplies. This paper discusses the application of a Pulse Compression procedure to identify the Hammerstein model of the saturation characteristic of FC inductors. The ability of the modeling approach to obtain a reliable model of non-linear FC inductors is tested through simulations in a case of practical interest, with comparisons to a literature behavioral model and its Taylor and Padé numerical approximations. 14:40 Accurate modeling of inductors working in nonlinear region in Switch-Mode Power Supplies with different load currents Alberto Oliveri, Matteo Lodi and Marco Storace. University of Genoa In this paper a nonlinear model is proposed to characterize ferrite-core inductors operating in saturation region in Switch-Mode Power Supplies (SMPSs). The model, identified through experimental measurements of inductor current and voltage, relates the inductance to the current flowing through the inductor and also to the SMPS load current. Results show that the model allows reproducing the inductor current with high accuracy, in different working conditions. 15:00 A Temperature Dependent Non-Linear Inductor Model for a DC/DC Boost Converter Daniele Scire'1, Samuele Rosato1, Giuseppe Lullo1 and Gianpaolo Vitale2. 1DEIM, Universita' di Palermo, 2National Research Council of Italy This paper is focused on the use of non-linear inductors in DC/DC switching converters, as well as their behaviour due to changes in current and temperature. The model of an inductor is set up on the basis of experimental data, which are automatically acquired by a virtual instrument; from those data, a polynomial curve describing the inductance variations is obtained. The analysis of the converter, performed by including the proposed model, is validated by experimental tests. 15:20 Loss Behavioral Modeling for Ferrite Inductors Giulia Di Capua, Nicola Femia and Kateryna Stoyka. University of Salerno This paper presents a new behavioral model of AC power loss for Ferrite Power Inductors (FPIs) used in Switch-Mode Power Supply (SMPS) applications, including the effects of saturation. The model has been identified by means of a genetic programming algorithm and a multi-objective optimization technique, given a large sets of power loss experimental measurements. The proposed AC power loss model uses the voltage and switching frequency imposed to the inductor as input variables, while the DC inductor current is used as a parameter expressing the impact of saturation. Experimental results prove the reliability of the power loss predictions for FPIs, also by correctly accounting for the impact of saturation. 15:40 Geometric Form Factors-based Power Transformers Design Giulia Di Capua and Nicola Femia. DIEM - University of Salerno A novel model for power transformers design is presented in this paper. It is based on the use of two Geometric Form Factors (GFFs) – namely KF and KC - associated to magnetic cores shape and material. The transformer non-linear magneto-electro-thermal model is solved numerically to identify the commercial magnetic core whose GFFs allow minimizing the size of a custom transformer, under given power loss and thermal specifications. The model provides the boundaries of the acceptability region in the plane KF-KC enabling a straight comparison among multiple feasible solutions compliant with given design constraints. The case study presented in the paper concerns the design of a custom power transformer for an isolated DC-DC converter. 14:00-16:00 Data conversion and signal processing Room #10  Chair: Ralf Sommer, IMMS GmbH, Germany 14:00 Controlled-Oscillator Optimization for Highly-Digital CMOS Time-Based Sensor-to-Digital Converter Architectures Elisa Sacco1, Jorge Marin1, Johan Vergauwen2 and Georges Gielen1. 1Katholieke Universiteit Leuven, 2Melexis This paper presents the theoretical analysis and comparison of two major highly-digital-oriented architectures for sensor interfaces. The first architecture is based on a phase-locked loop, while the second one is count-based. These two time-based topologies have a different working principle, which leads to different VCO requirements in terms of gain linearity (voltage-to-frequency, V-to-f, or voltage-to-period, V-to-T, linearity). To validate the theoretical analysis, a state-variable-based Matlab model has been developed for both architectures confirming that using a VCO with the optimal linear transfer characteristic (V-to-T or V-to-f) is fundamental to achieve the maximum SQNR. 14:20 Analysis and simulation of chopper stabilization techniques applied to Delta-Sigma converters Alessandro Catania, Andrea Ria, Simone Del Cesta, Massimo Piotto and Paolo Bruschi. University of Pisa MATLAB/Simulink modeling of offset and flicker noise in Delta-Sigma modulators has been developed, providing a fast tool for the estimation of ADC performances. Since high accuracy and resolution are fundamental in sensor applications, a brief analysis of the main noise sources in second order Delta- Sigma modulators is presented, together with the typical solutions found in the literature. Generalization of system-level chopper techniques for the rejection of the converter overall offset and low-frequency noise has been proposed and their effectiveness is evaluated by means of high-level simulations. 14:40 New Reconfigurable Universal SISO Biquad Filter Implemented by Advanced CMOS Active Elements Roman Sotner1, Lukas Langhammer1, Ondrej Domansky1, Jiri Petrzela1, Jan Jerabek1 and Tomas Dostal2. 1Dept. of Radio electronics, Faculty of Electrical Engineering and Communication, Brno University of Technology, 2Dept. of Technical Studies, College of Polytechnics Jihlava This paper presents new topology of fully universal multi-parametrically electronically reconfigurable reconnection-less single-input single-output (SISO) voltage-mode biquad. The proposed structure offers all five second-order transfers functions (high-pass, band-pass, low-pass, band-reject and all-pass) simultaneously available by proper electronic configuration as well as setting of pole frequency and quality factor. Special active device called controlled-gain current-controlled differential difference current conveyor of second generation has been designed in ON Semiconductor 0.35 um CMOS technology for purposes of modeling and simulation tests of proposed filter. PSpice simulations confirm intended behavior of the topology. 15:00 System of Standard Approximations for Optimum Frequency Filter Design Karel Hajek. University of Defence In many practical cases, the designers have to solve the approximation tasks for the design and implementation of the frequency filters, usually choosing the standard approximation type. This concerns the design of both analogue filters and digital IIR filters. Unfortunately, in common practice, the type of approximation is not optimally chosen in many cases. Usually, designers choose a well-known standard approximation, such as Butterworth, without a deeper and more consistent assessment of the essential properties. The resulting implementation of the frequency filter, of course, may not have optimal properties. The presented article offers a rather comprehensive system of standard approximations, from which it is possible to select the optimal solution for this task on the basis of some practical criteria and shows these procedures. 15:20 Design and Error Analysis of Inductance Multiplier via Symbolic Algorithms Jiri Vavra, Dalibor Biolek and Zdenek Kolka. Czechia University of defence, Brno University of Technology A procedure supporting the design and optimization of analog circuits is described. It is based on symbolic analysis of the respective linearized model with the aim of revealing the major factors influencing the non-ideal behavior of the designed device. SNAP 3, a powerful tool for the approximate symbolic analysis of circuits containing assorted types of active building blocks, plays a key role in this process. The procedure is illustrated on an example of inductance multiplier. 15:40 A Low-power, Bootstrapped Sample and Hold Circuit with Extended Input Range for Analog-to-Digital Converters in CMOS 0.18um Ahmad Mohammadi and Mohammad Chahardori. Department of Electrical Engineering, Science and Research Branch, Islamic Azad University, Tehran, Iran In this paper, an input range extended sample and hold circuit is proposed. This input range extension is achieved through connecting the body of the transistor, which charges the bootstrap capacitor, to its source. This structure allows the sampling section to accept a higher input voltage. Also, the bootstrap capacitor value and transistors sizes are scaled down and power consumption is reduced. The proposed method maintains the overall performance of the sample and hold circuit in analogy to previously reported works while it increases the amplitude of the differential input signal up to 1.8 V in 0.18 μm CMOS technology. The proposed circuit is simulated using 0.18um standard CMOS technology. The sample and hold circuit reaches a peak signal-to-noise and distortion ratio (SNDR) of 64.9 dB for 99.4 MHz input signal with a full-scale voltage equal to 1.8 V. 14:00-16:00 Sensing and Biomedical Circuits II Room #115  Chair: Piero Malcovati, University of Pavia, Italy 14:00 Super-capacitors for implantable medical devices with wireless power transmission P. Mendoza Ponce, B. John, D. Schroeder, W. Krautschneider TU Hamburg-Harburg, Germany Patients using implantable devices with wireless power transmission (such as inductive telemetry) as the energy source are required to carry external hardware and antennas on their body continuously during the monitoring period. This discomfort can be reduced by integrating tiny super-capacitors as an energy source for the device. The external wireless telemetry unit used to activate and interrogate the implantable device charges the super capacitors integrated on it. When the wireless telemetry unit is removed, the super capacitor powers the implantable device. This paper shows the benefits of integrating super capacitors onto an existing pressure sensing medical implant that utilises an inductive telemetry link. Test results show that the implant can be powered for a full day using an 88 mF super capacitor. This super capacitor can be fully charged using the inductive telemetry link at a wireless distance of 20 cm in 81 seconds. 14:20 Design and Modelling of a Super-Regenerative Receiver for Medical Implant Devices N. Pekçokgüler1, G. Dündar1, C. Dehollain2 1Bogazici University, Turkey; 2EPFL, Switzerland Medical implant devices have been widely used in recent years. The Super-Regenerative Receiver has been on preferred architecture due to its power advantage over other architectures. We present a detailed analysis of the circuits and their equivalent models to be used in system level design of a Super-Regenerative Receiver in this paper. Designs were carried out in UMC 180nm process with a center frequency of 416MHz for MedRadio band. The study is concluded with the simulation results of the circuits and the equivalent models. 14:40 A Fully Fail-Safe Capacitive-Based Charge Metering Method for Active Charge Balancing in Deep Brain Stimulation R. Ranjandish1, O. Shoaei2, A. Schmid1 1EPFL, Switzerland; 2University of Tehran, Iran Related to safety issues, charge balancing is a major concern in neural and functional electrical stimulation. This paper presents a capacitive-based charge metering method as a low-power and precise charge balancing method used in Deep Brain Stimulation (DBS). In contrast to the previously presented capacitive-based charge metering methods, the proposed method does not need any precise and high-speed comparator for net-zero charge detection. It is proven that this method is insensitive to the delay and the offset of its components. Consequently, using ultra-low power components in the charge balancer is feasible. Furthermore, the proposed method properly supports any stimulation mode and waveform. The proposed approach along with voltage and current mode pulse generators was validated in a 0.9\% saline solution by using a DBS lead. 15:00 Current Controlled CMOS Stimulator with Programmable Pulse Pattern for a Retina Implant P. Raffelberg1, R. Burkard1, R. Viga1, W. Mokwa2, P. Walter2, A. Grabmaier3, R. Kokozinski3 1University of Duisburg-Essen, Germany; 2RWTH Aachen University, Germany; 3Fraunhofer IMS Duisburg, Germany In this work the constant current stimulator of a new epiretinal implant is presented. It consists of a digital waveform generator device, which allows to modify the pulse pattern via a programming interface, a digital‚Äìto‚Äìcurrent converter, which translates the digital waveform into current pulses with adjustable amplitude, and an output driver, which combines the function of an electrode multiplexer and a high voltage current source for driving large resistive loads. For each of those subcircuits the simulated performance and its designed layout is presented. 15:20 A Laser Diode-Based Wireless Optogenetic Headstage A. Mesri1, A. Cunha2, Ø. Martinsen2, M. Sampietro1, G. Ferrari1 1Politecnico di Milano, Italy; 2University of Oslo, Norway A power efficient, battery powered optogenetic headstage for doing in-vivo experiments with freely moving genetically modified animals is presented. The proposed system is designed with commercial off-the-shelf components, and is based on a Bluetooth Low Energy (BLE) System-on-Chip (SoC) with an integrated antenna and a programmable ARM Cortex-M3 microprocessor core able to control the circuit. The optical signal is generated using a compact laser diode (LD) suitable for a wearable headstage. LD produces light in a highly concentrated way considerably improving the LD-optical fiber coupling efficiency. The proposed optogenetic system is shown to provide 120 mW/mm2 at the fiber tip with a current consumption of 60mA, considerably lower than LED-based systems. The system is remotely controlled by a smartphone app where the user can define optical stimulations patterns settings (optical power, frequency, duty cycle, etc.). It is also powerful enough to be ready to house additional optogenetics functionalities, like electrochemical sensing of the cell response, without significant modifications, thus being the basis of an integrated optogenetic platform. 15:40 An Active Charge Balancing Method Based on Chopped Anodic Phase R. Ranjandish, A. Schmid EPFL, Switzerland A new method for safe electrical neural stimulation is proposed. A negative feedback is used to automatically produce short anodic pulses according to the remaining voltage. The period of the short anodic pulses varies according to the remaining voltage. Thanks to the structure of the static comparator, the system produces pulses with high duty-cycle at the beginning of the anodic phase and low duty-cycle at the end of the anodic phase. Hence, the system can accurately balance the charge. In contrast with previous methods based on the chopped anodic phase, this method employs a new structure that reduces the area of charge balancer for integration and increases the accuracy for a safe electrical stimulation. Lowering the power consumption of the charge balancing circuit is another outcome of the proposed method. An integrated circuit implementing the proposed method is designed using a 0.18 $\mu$m technology. The simulation results prove the accuracy and proper performance of the proposed method in both current and voltage mode stimulation. 14:00-16:00 Emerging and non-CMOS technologies Atrium  Chair: Jan Chochol, ON Semiconductor, Czech Republic 14:00 Fabrication of Full-3D Printed Electronics RF Passive Components and Circuits A. Salas Barenys1, N. Vidal1, J. Sieiro1, J. Lopez Villegas1, B. Medina2, F. Ramos2 1University of Barcelona, Spain; 2Francisco Albero S.A.U. (FAE), Spain This paper presents a process for full-3D circuit and RF passive component fabrication based on two main steps: additive manufacturing of the plastic or ceramic substrate, through a stereolitographic 3D printer, and a copper electroless plating metallization process. The metallization results are discussed in terms of resistivity, comparing hem to the State-of-the-Art on 3D printed electronics. The capabilities and accuracy of the process have been demonstrated and discussed through the fabrication of conical inductors. 14:20 Modeling and Simulation of Novel GaN-based Light Emitting Transistor for Display Applications S. Lee, I. Yun Yonsei University, South Korea For the research of next-generation displays, technology of shrink device size is the most attractive and important technology. It is possible to manufacture high-performance display products by using high integrated devices such as mobile application. However, there is a certain limitation to the downsizing technology. Therefore, new device synthesis techniques are becoming important. In this paper, we propose a device design that combines inorganic material based light-emitting diode (LED) and thin-film transistor (TFT). By integrating the LED and TFT devices into one region, it is possible to highly integrate the devices, which can greatly reduce the size of the entire device. To investigate a possibility of device implementation, technology computer-aided design (TCAD) simulation is used. After that, an optical and electrical characteristic of the device are analyzed. Finally, the light-emitting transistor (LET) is proposed. 14:40 Improving Deep Learning with a customizable GPU-like FPGA-based accelerator M. Gagliardi, E. Fusella, A. Cilardo University of Napoli Federico II, Italy An ever increasing number of challenging applications are being approached using Deep Learning, obtaining impressive results in a variety of different domains. However, state-of-the-art accuracy requires deep neural networks with a larger number of layers and a huge number of different filters with millions of weights. GPU- and FPGA-based architectures have been proposed as a possible solution for facing this enormous demand of computing resources. In this paper, we investigate the adoption of different architectural features, i.e. SIMD paradigm, multithreading, and non-coherent on-chip memory for Deep Learning oriented FPGA-based accelerator designs. Experimental results on a Xilinx Virtex-7 FPGA show that the SIMD paradigm and multithreading can lead to an improvement in the execution time up to 5x and 3.5x, respectively. A further enhancement up to 1.75x can be obtained using a non-coherent on-chip memory. 15:00 Analysis and Verification of Identical-Order Mixed-Matrix Fractional-Order Capacitor Networks A. Kartci1, A. Agambayev2, N. Herencsar1, K. Salama2 1Brno University of Technology, Czech Republic; 2King Abdullah University of Science and Technology, Saudi Arabia In the open literature while capacitors are introduced with -90 degrees phase angle, here we described our fabricated polymer composite, mixed matrix, as a fractional-order capacitor (FoC). The effect on phase and pseudo-capacitance using a detailed numerical and experimental study of series and parallel connections of three identical-order FoCs is shown. The used devices have excellent feature such as constant phase angle in the frequency range 0.2 MHz-20 MHz. SMACD 2018 POSTERS (during all Coffee Breaks of July 3rd & 4th and the morning Coffee Break of July 5th  Chair: Fernando García Redondo, Arm Ltd., UK 10:00-10:20 & 16:00-16:20 A Cell-Based Fractional-N Phase-Locked Loop Compiler C. Lee, S. Huang National Tsing Hua University, Taiwan In this work, we present the first cell-based Fractional-N Phase-Locked Loop (PLL) compiler, according to the best of our knowledge. Unlike its previous integer-N PLL compiler, a target clock frequency can be generated precisely with an almost arbitrary input reference clock frequency. For example, 1GHz output clock can be generated from a given 17.33MHz reference clock. With a search engine, such a compiler can find a small-area as well as low-power PLL configuration within minutes. We also have verified its ability for two process nodes (i.e., 90nm and 180nm) by transistor-level simulation on seven test-case PLL macros generated by this compiler. Experimental results show that they can indeed function correctly under extreme PVT conditions. 10:00-10:20 & 16:00-16:20 Mixed Design of SPAD Array Based TOF for Depth Camera and Unmanned Vehicle Applications W. Shi, A. Pan Shenzhen University, China Depends on the increasing requirements of unmanned vehicle mobile Lidar systems, this paper presents a system design based on pulsed TOF depth image cameras. The design has a detection range of 300m and detecting resolution of 1.5cm. Pixels are made of SPAD. Meanwhile, innovative structure of multi-pixel sharing TDC is proposed, chip area is greatly reduced and the fill factor of light-sensing surface area is optimized. The TCSPC module with the functionalities of receiving each photon, measuring photon flight time and processing depth information is also included in the chip design. Based on 0.13μm CIS CMOS technology, the entire design indicates high integration with low power and fast response features. 10:00-10:20 & 16:00-16:20 Modeling of Reference Injection Based Low-Power All-Digital Phase-Locked Loop for Bluetooth Low-Energy Applications in LabVIEW M. Rehman, N. Ahmad, I. Ali, S. Oh, A. Hejazi, K. Lee Sungkyunkwan University, South Korea This paper presents a modeling of All Digital Phased-Lock Loop (ADPLL) based on reference injection (RI) technique in LabVIEW. ADPLL is one of the attractive solutions due to its low design complexity and low power consumption which makes it suitable candidate for low power IoT devices. The RI based design eliminates the strict requirements of time to digital converter (TDC) in traditional ADPLL structure which significantly reduces the design complexity and consumes low power. By utilizing the efficient system design capabilities offered by the LabVIEW environment, a RI based ADPLL is modeled in LabVIEW to evaluate the design and analyze its performance. The system level simulation of the ADPLL is significantly meaningful for the research and design process in a comprehensive way. The simulation results are also presented for the 2.4 GHz reference injection based ADPLL from a reference frequency of 32MHz. 10:00-10:20 & 16:00-16:20 SC Filter Optimization Performance by Hybrid Simplex Algorithm J. Náhlík, J. Hospodka, O. Subrt CTU in Prague, Czech Republic The paper investigates the performance of the Nelder-Mead (NM) and Differential Evolution (DE) hybrid al- gorithm applied to switched capacitor (SC) filter optimization. The performance is investigated on a design of four biquadratic filters and the results are compared to the original algorithm performances and other hybrid algorithms performances. 10:00-10:20 & 16:00-16:20 A Low Power Priority Encoding Technique with Address-Encoder and Reset-Decoder for an Improved Hierarchical Asynchronous Detector C. Lee, C. Kim, H. Lim, S. Kim, M. Song Dongguk University, South Korea A novel priority encoding technique with an address-encoder and reset-decoder(AERD) for a hierarchical asynchronous detector is discussed. Conventionally, an asynchronous detector has a slow operating speed, because it checks and takes the only activated cells. In order to enhance the data transfer rates, an improved hierarchical asynchronous detector is proposed. Further, a low power priority encoding technique with an AERD is also described. A test chip to verify the proposed technique has been fabricated with a Hynix 0.18um CMOS technology. The power consumption is about 7.5mW, which is much smaller than the conventional ones at the same patterns. 10:00-10:20 & 16:00-16:20 Kriging Metamodeling-Assisted Multi-Objective Optimization of CMOS Current Conveyors M. Kotti1, M. Fakhfakh2, E. Tlelo-Cuautle3 1University of Sousse, Tunisia, 2University of Sfax, Tunisia, 3INAOE, Mexico In this brief, we deal with the generation of the Pareto front for multi-objective analog circuit sizing optimization. The main idea of the proposed work consists of using metamodels of the considered performances to generate the set of nondominated solutions. These models serve as evaluators. They offer several advantages, mainly their high precision for reproducing the real behavior of the considered performances, and their very rapid evaluation, when compared to their counterpart, i.e. the in-loop-based sizing technique. Multiobjective particle swarm optimization (MOPSO) technique is used as the optimization metaheuristic. The proposed approach is first applied to some mathematical test functions, then, we consider the optimal sizing of MOS current conveyors, where two conflicting objectives are considered, namely maximizing the current transfer cutoff frequency (fci) and minimizing the parasitic X-port resistance (Rx). Obtained results are compared to those reached using the conventional in-loop optimization technique. Hspice simulations, using AMS 0.35μm CMOS technology, are given to highlight these reached results. 10:00-10:20 & 16:00-16:20 2D Bifurcations and Chaos in Nonlinear Circuits: A Parallel Computational Approach W. Marszalek1, J. Sadecki2 1Rutgers University, United States, 2Opole University of Technology, Polando This paper deals with parallel computation of 2D bifurcation diagrams in nonlinear oscillating circuits. When two parameters in such circuits vary simultaneously, then a significant computational effort is needed to capture all the details of the obtained bifurcation diagrams. Therefore, parallel computing seems to be a natural approach as, in a typical problem, we deal with solving of a system of ordinary differential equations tens or hundreds of million of times. One particular system of three differential equations from plasma science (electric arc RLC circuit) is used as a test example. 10:00-10:20 & 16:00-16:20 System-Level Behavioral Model of a 12-bit 1.5-bit per Stage Pipelined ADC Based on Verilog-AMS V. Ponce-Hinestroza1, V. Gonzalez-Diaz1, J. Castaneda Camacho1, G. Mino-Aguilar1, E. Bonizzoni2 1Benemérita Universidad Autónoma de Puebla, Mexico, 2University of Pavia, Italy This document presents a system-level behavioral model of a 12-bit 1.5-bit/stage pipelined ADC based on Verilog- AMS that can be used in the CMOS circuit design activities. It was developed with one of the currently most used EDA tools, Cadence Virtuoso, the versatility of this software allowed to create a model that consist of subsystems at circuit level described in Verilog, Verilog-A and SPICE, in others words, Verilog-AMS. The model was tested in time and frequency, the results exhibit a SQNR of 73.7 dB and an ENoB of 11.5 bits when ideal parameters are present. 10:00-10:20 & 16:00-16:20 Reconfiguring Passive Linear Systems C. Onete1, M. Onete2 1NXP Semiconductors, Netherlands, 2University of Limoges, France In this paper it is shown that passive linear circuits can be easily reconfigured using equivalent electrical signals. The method is based on the cycle description of the passive circuits, and it can be extended to any linear system equivalent to an electrical circuit as e.g. microfluidic networks, heat systems, etc.